EPM5192AGC vs EPM5192-1LC 比較

詳細な並列比較: EPM5192AGC メーカー: Altera および EPM5192-1LC メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5192AGC EPM5192-1LC
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete Obsolete
在庫状況 In Stock In Stock
単価(USD) $56.00 $19.40
Family MAX 5000 (High-Speed, High-Density MAX 5000 Devices) MAX 5000
Device Type UV-Erasable / OTP Complex PLD (EPLD) CPLD (Complex Programmable Logic Device)
Macrocells 192 192
Logic Density High-density (per MAX 5000 family definition) —
Architecture CMOS, sum-of-products with macrocell output logic —
Process Technology CMOS UV EPROM, erasable windowless
パッケージ 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) 64-pin Ceramic J-Lead Chip Carrier (LC)
Speed Grade Suffix C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) —
動作温度 [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
Programmability UV-erasable (windowed package) / One-Time-Programmable (windowless variant) —
Security Bit Programmable security bit (per MAX 5000 family) —
電源電圧 [DATA_NEEDED: VCC nominal and tolerance] 5 V
実装タイプ Through-hole (Pin Grid Array) Surface Mount
RoHS ステータス Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) Non-compliant (ceramic windowless package, lead-bearing termination)
Lifecycle Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) —
Programming Support MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers —
Usable Gates — 3,750
Logic Array Blocks (LABs) — 4
User I/O Pins — 64
Maximum Operating Frequency — 62.5 MHz
Propagation Delay (tpd) — [DATA_NEEDED: -1 speed grade tpd in ns]
Programmable Interconnect — PIA (Programmable Interconnect Array)
JTAG Boundary Scan — IEEE 1149.1 compliant

データシート&リソース

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