EPM5192AGC vs EPM5192AGC-20 比較

詳細な並列比較: EPM5192AGC メーカー: Altera および EPM5192AGC-20 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5192AGC EPM5192AGC-20
ブランド Altera Intel
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete Obsolete
在庫状況 In Stock In Stock
単価(USD) $56.00 $9.95
Family MAX 5000 (High-Speed, High-Density MAX 5000 Devices) MAX 5000
Device Type UV-Erasable / OTP Complex PLD (EPLD) EPLD (EEPLD, UV-erasable)
Macrocells 192 192
Logic Density High-density (per MAX 5000 family definition) —
Architecture CMOS, sum-of-products with macrocell output logic —
Process Technology CMOS —
パッケージ 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) PGA-132 (ceramic windowed, 'GC')
Speed Grade Suffix C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) —
動作温度 [DATA_NEEDED: operating temperature range] 0C to 70C (commercial)
Programmability UV-erasable (windowed package) / One-Time-Programmable (windowless variant) —
Security Bit Programmable security bit (per MAX 5000 family) Yes (pattern read-back protected)
電源電圧 [DATA_NEEDED: VCC nominal and tolerance] —
実装タイプ Through-hole (Pin Grid Array) Through-hole (PGA socket)
RoHS ステータス Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) [DATA_NEEDED: RoHS status - ceramic PGA windowed parts are typically pre-RoHS]
Lifecycle Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) —
Programming Support MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers —
Usable Gates — 12,000
Propagation Delay (tPD) — 20 ns
Counter Frequency (fCNT) — 100 MHz (max)
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Logic Array Blocks (LABs) — 8
Dedicated I/O Pins — 96
Programming Interface — IEEE 1149.1 JTAG
In-System Programmability — Yes (5 V ISP)

データシート&リソース

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