EPM5192AJC-15 vs EPM5192GC1 比較
詳細な並列比較: EPM5192AJC-15 メーカー: Intel および EPM5192GC1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192AJC-15 | EPM5192GC1 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.85 | $24.50 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | — |
| Logic Capacity | 100% connectivity, sum-of-products PLA architecture | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V |
| 動作温度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| パッケージ | 84-pin PLCC (J-lead, ceramic, non-windowed) | — |
| 実装タイプ | Surface Mount | Through-hole (PGA) |
| Programmability | UV-erasable (windowed variant) / One-Time-Programmable | — |
| Toolchain | MAX+PLUS II | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | unknown |
| ピン数 | 84 | — |
| User I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Speed Grades Available | -15, -20, -25 (this part: -15) | — |
| Configuration Memory | EPROM (UV-erasable) | — |
| Macro Cells | — | 192 |
| Usable Gates | — | 3,750 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Programming Technology | — | UV-Erasable / OTP EPROM |
| Package Type | — | Ceramic PGA (Pin Grid Array) |
| Logic Elements | — | 192 macrocells with AND/OR array |
| Process Technology | — | EPROM-based CMOS |
| Propagation Delay | — | [DATA_NEEDED: tpd specification] |
| ピン数 | — | [DATA_NEEDED: pin count for GC1 PGA package] |
| Development Tool | — | Altera MAX+PLUS II |