EPM5192AQC-1 vs EPM5192AGC 比較

詳細な並列比較: EPM5192AQC-1 メーカー: Altera および EPM5192AGC メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5192AQC-1 EPM5192AGC
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete Obsolete
在庫状況 In Stock In Stock
単価(USD) $17.40 $56.00
Family MAX 5000 MAX 5000 (High-Speed, High-Density MAX 5000 Devices)
Device Type One-Time Programmable (OTP) CPLD UV-Erasable / OTP Complex PLD (EPLD)
Macrocells 192 192
Logic Elements / Logic Array Blocks [DATA_NEEDED: number of LABs] —
Propagation Delay (tPD) 40 ns —
Maximum Operating Frequency [DATA_NEEDED: fMAX value] —
User I/O Pins 64 —
Dedicated Inputs 7 —
Total Inputs / Outputs 72 inputs / 64 outputs —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Nominal Supply Voltage 5 V —
動作温度範囲 0 °C to +70 °C (commercial) —
パッケージ PQFP-100 (Plastic Quad Flat Pack) 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless)
Terminal Pitch 0.635 mm —
Technology CMOS, UV-Erasable / OTP EPROM —
Configuration Method One-Time Programmable (OTP) / UV-Erasable —
実装タイプ Surface Mount Through-hole (Pin Grid Array)
RoHS ステータス [DATA_NEEDED: RoHS status] Non-compliant (ceramic PGA contains lead; legacy military/industrial grade)
Lead-Free [DATA_NEEDED: lead-free status] —
Logic Density — High-density (per MAX 5000 family definition)
Architecture — CMOS, sum-of-products with macrocell output logic
Process Technology — CMOS
Speed Grade Suffix — C (commercial grade; specific pin-to-pin delay varies by base number -15/-20)
動作温度 — [DATA_NEEDED: operating temperature range]
Programmability — UV-erasable (windowed package) / One-Time-Programmable (windowless variant)
Security Bit — Programmable security bit (per MAX 5000 family)
電源電圧 — [DATA_NEEDED: VCC nominal and tolerance]
Lifecycle — Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs)
Programming Support — MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers

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