EPM5192GC1 vs EPM5192JC 比較
詳細な並列比較: EPM5192GC1 メーカー: Altera および EPM5192JC メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192GC1 | EPM5192JC |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $24.50 | $16.40 |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 192 | — |
| Usable Gates | 3,750 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Programming Technology | UV-Erasable / OTP EPROM | — |
| Package Type | Ceramic PGA (Pin Grid Array) | — |
| Logic Elements | 192 macrocells with AND/OR array | — |
| Process Technology | EPROM-based CMOS | CMOS EPROM (UV-erasable) |
| 動作温度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: commercial / industrial / military grade] |
| Propagation Delay | [DATA_NEEDED: tpd specification] | [DATA_NEEDED: tpd spec by speed grade] |
| ピン数 | [DATA_NEEDED: pin count for GC1 PGA package] | — |
| 実装タイプ | Through-hole (PGA) | Surface Mount |
| RoHS ステータス | unknown | [DATA_NEEDED: original Altera marking not RoHS] |
| Development Tool | Altera MAX+PLUS II | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| パッケージ | — | 68-pin PLCC (JC) windowed ceramic |
| Programming Method | — | UV-erase + EPROM programmer |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| 電源電圧 | — | [DATA_NEEDED: VCC nominal] |