EPM5192GC84-1 vs EPM5192AGC 比較

詳細な並列比較: EPM5192GC84-1 メーカー: Altera および EPM5192AGC メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5192GC84-1 EPM5192AGC
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete Obsolete
在庫状況 In Stock In Stock
単価(USD) $14.20 $56.00
Family MAX 5000 MAX 5000 (High-Speed, High-Density MAX 5000 Devices)
Product Type UV-Erasable/OTP Complex PLD (CPLD) —
Technology CMOS (EPROM-cell based) —
Macrocells 192 192
Propagation Delay (tPD) 40 ns (speed grade -1) —
最大クロック周波数 50 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Dedicated Inputs 7 —
User I/O Pins 64 —
Total Inputs / Outputs 72 inputs / 64 outputs —
Architecture Shared input/clock and shared product terms CMOS, sum-of-products with macrocell output logic
パッケージ 84-pin PGA (Pin Grid Array), WPGA code 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless)
Temperature Grade Commercial —
実装タイプ Through-hole (PGA socket) Through-hole (Pin Grid Array)
RoHS ステータス Compliant (per third-party distributor listing) Non-compliant (ceramic PGA contains lead; legacy military/industrial grade)
Programming Method UV erasure (quartz window) + EPROM programmer —
Logic Element Type Macrocells with AND/OR array —
Device Type — UV-Erasable / OTP Complex PLD (EPLD)
Logic Density — High-density (per MAX 5000 family definition)
Process Technology — CMOS
Speed Grade Suffix — C (commercial grade; specific pin-to-pin delay varies by base number -15/-20)
動作温度 — [DATA_NEEDED: operating temperature range]
Programmability — UV-erasable (windowed package) / One-Time-Programmable (windowless variant)
Security Bit — Programmable security bit (per MAX 5000 family)
電源電圧 — [DATA_NEEDED: VCC nominal and tolerance]
Lifecycle — Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs)
Programming Support — MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers

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