EPM5192GM-1 vs EPM5192IC-1 比較
詳細な並列比較: EPM5192GM-1 メーカー: Altera および EPM5192IC-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192GM-1 | EPM5192IC-1 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $27.80 | $13.95 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Logic Cells | 192 | — |
| Propagation Delay (tpd) | 55 ns | — |
| Process Technology | CMOS | — |
| Programmable Element | UV-erasable EPROM | — |
| パッケージ | CPGA-84 (Windowed Ceramic PGA) | 68-pin ceramic J-lead (IC-1 suffix) |
| ピン数 | 84 | — |
| 電源電圧 | [DATA_NEEDED: VCC nominal] | — |
| 動作温度範囲 | [DATA_NEEDED: commercial/industrial/military grade] | — |
| Programmable Macrocells | 192 | — |
| User I/O Pins | [DATA_NEEDED: user I/O count] | — |
| 実装タイプ | Through-Hole (Pin Grid Array socket) | — |
| RoHS Compliance | unknown (legacy ceramic PGA) | — |
| Lead-Free Status | unknown | — |
| Programming Interface | Altera ByteBlaster / JEDEC bitstream | JTAG / IEEE Std 1149.1 boundary scan |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| Macrocells | — | 192 |
| Usable Gates | — | 3750 |
| Dedicated Inputs | — | 7 |
| I/O Pins | — | 64 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (max, -1 speed grade) |
| Counter Frequency (fCNT) | — | 76.9 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| 動作温度 | — | -40C to +85C (industrial) |
| Technology | — | CMOS, UV-erasable, in-system programmable |
| Security Bit | — | Yes (design protection) |
| Supply Current (Icc, typical) | — | [DATA_NEEDED: Icc] mA |
| Output Drive Current (IOH/IOL) | — | [DATA_NEEDED: IOH/IOL] mA |