EPM5192GM vs EPM5192GM883B-2 比較
詳細な並列比較: EPM5192GM メーカー: Altera および EPM5192GM883B-2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192GM | EPM5192GM883B-2 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $58.00 | $142.00 |
| Product Family | MAX 5000 | — |
| Device Type | UV Erasable Programmable Logic Device (PLD) | CPLD (Complex Programmable Logic Device), UV-erasable |
| Technology | CMOS | 5 V CMOS |
| Number of Macrocells | 192 | — |
| Usable Gates | 3,750 | — |
| Pin-to-Pin Delay (tPD) | 15 ns (fastest speed grade); 55 ns (this part) | — |
| Counter Frequency (fCNT) | up to 76.9 MHz | — |
| Propagation Delay (tPD, this part) | 55 ns | — |
| パッケージ | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) | 84-pin Ceramic Pin Grid Array (CPGA), code S-CPGA-P84 |
| 実装タイプ | Through-Hole (PGA) | Through-hole PGA socket |
| Erasure Method | UV (windowed ceramic package) | — |
| 電源電圧 | [DATA_NEEDED: typical VCC range] | — |
| Maximum User I/O | [DATA_NEEDED: exact I/O count for CPGA-84] | — |
| 動作温度 | [DATA_NEEDED: commercial/industrial/military grade] | [DATA_NEEDED: operating temperature range] |
| RoHS ステータス | Non-compliant (contains lead in ceramic PGA) | non_compliant (ceramic CPGA with MIL-STD-883 screening) |
| Process Node | [DATA_NEEDED: CMOS process geometry] | — |
| Programming Interface | JTAG-compatible (per MAX 5000 family) | — |
| Family | — | MAX 5000 |
| Macrocells | — | 192 |
| Propagation Delay (tPD) | — | 45 ns (-2 speed grade) |
| Maximum Internal Clock Frequency | — | 33.3 MHz |
| Supply Voltage (VCC, nominal) | — | 5 V |
| Dedicated Inputs | — | 7 |
| User I/O Pins | — | 64 |
| Package Outline | — | 28.45 mm square (approx.) |
| Military Screening | — | MIL-STD-883 (per '883' suffix) |
| JEDEC Package Code | — | S-CPGA-P84 |