EPM5192JC-2 vs EPM5192JC-1 比較
詳細な並列比較: EPM5192JC-2 メーカー: Altera および EPM5192JC-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192JC-2 | EPM5192JC-1 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $22.50 | $22.40 |
| Device Family | MAX 5000 | — |
| Product Type | UV-erasable Programmable Logic Device (PLD) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| User I/O Pins | 64 | 84 |
| Dedicated Inputs | 7 | — |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 45 ns | 40 ns (speed grade -1) |
| 最大クロック周波数 | 40 MHz | — |
| Process Technology | CMOS | — |
| パッケージ | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) | — |
| 実装タイプ | Surface Mount | — |
| Number of Terminals | 84 | — |
| Programming Method | UV-erase / EPROM | — |
| 動作温度範囲 | [DATA_NEEDED: operating temperature range] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | — |
| Family | — | MAX 5000 |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Technology | — | CMOS, UV-Erasable / OTP |
| Usable Gates | — | 3750 |
| Maximum Internal Frequency (fMAX) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Package Type | — | 84-pin Ceramic Quad Flat Pack (CQFP), windowed |
| JEDEC Package Code | — | S-CQCC-J84 |
| 動作温度 | — | 0 C to +70 C (commercial) |
| Configuration Memory | — | UV-EPROM (erasable under UV lamp) |
| Programming Interface | — | Altera MAX programming interface (parallel, pre-JTAG for this family) |
| Process | — | CMOS EPROM |
| I/O Standard | — | TTL/CMOS 5 V compatible |