EPM5192JC vs EPM5192GC1 比較
詳細な並列比較: EPM5192JC メーカー: Intel および EPM5192GC1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192JC | EPM5192GC1 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $16.40 | $24.50 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Series | EPM5192 (Classic / MAX-class) | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect Architecture | Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS EPROM (UV-erasable) | EPROM-based CMOS |
| パッケージ | 68-pin PLCC (JC) windowed ceramic | — |
| 実装タイプ | Surface Mount | Through-hole (PGA) |
| Programming Method | UV-erase + EPROM programmer | — |
| Non-Volatile Configuration | Yes (EPROM cell array) | — |
| Logic Family | Classic CPLD (EPM5xxx series) | — |
| 動作温度 | [DATA_NEEDED: commercial / industrial / military grade] | [DATA_NEEDED: operating temperature range] |
| 電源電圧 | [DATA_NEEDED: VCC nominal] | — |
| Propagation Delay | [DATA_NEEDED: tpd spec by speed grade] | [DATA_NEEDED: tpd specification] |
| RoHS ステータス | [DATA_NEEDED: original Altera marking not RoHS] | unknown |
| Family | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 192 |
| Usable Gates | — | 3,750 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Programming Technology | — | UV-Erasable / OTP EPROM |
| Package Type | — | Ceramic PGA (Pin Grid Array) |
| Logic Elements | — | 192 macrocells with AND/OR array |
| ピン数 | — | [DATA_NEEDED: pin count for GC1 PGA package] |
| Development Tool | — | Altera MAX+PLUS II |