EPM5192JC1 vs EPM5192JC 比較
詳細な並列比較: EPM5192JC1 メーカー: Intel および EPM5192JC メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192JC1 | EPM5192JC |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $48.30 | $16.40 |
| Family | MAX 5000 (MAX 5xxx CPLD) | — |
| Manufacturer | Intel (formerly Altera Corporation) | — |
| Macro Cells | 192 | — |
| Usable Gates | 3750 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | — |
| Process Technology | 0.5 µm CMOS, UV-erasable EPROM | CMOS EPROM (UV-erasable) |
| Propagation Delay (typ) | [DATA_NEEDED: propagation delay in ns] | — |
| I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| パッケージ | [DATA_NEEDED: exact package from datasheet] | 68-pin PLCC (JC) windowed ceramic |
| 実装タイプ | [DATA_NEEDED: surface mount or through-hole] | Surface Mount |
| 動作温度 | [DATA_NEEDED: operating temp range] | [DATA_NEEDED: commercial / industrial / military grade] |
| Programming Interface | JTAG-compatible (Altera MAX 5xxx) | — |
| Logic Blocks (LABs) | 24 (8 macrocells per LAB) | — |
| RoHS ステータス | unknown | [DATA_NEEDED: original Altera marking not RoHS] |
| AEC-Q100 | not_applicable | — |
| Lifecycle | Obsolete - last-time-buy stock only at franchised distributors | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Programming Method | — | UV-erase + EPROM programmer |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| 電源電圧 | — | [DATA_NEEDED: VCC nominal] |
| Propagation Delay | — | [DATA_NEEDED: tpd spec by speed grade] |