EPM5192JI-1 vs EPM5192JC-1N 比較
詳細な並列比較: EPM5192JI-1 メーカー: Intel および EPM5192JC-1N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192JI-1 | EPM5192JC-1N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $17.40 | $19.85 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CMOS UV-Erasable Programmable Logic Device (PLD / EPLD) | CPLD - Complex Programmable Logic Device |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Propagation Delay (tPD) | 55 ns | 40 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | 4.75 V to 5.25 V |
| Process Technology | CMOS EPROM | — |
| パッケージ | 84-pin JLCC (Windowed ceramic J-lead) | 84-pin Ceramic Quad Flat Pack (CQFP) |
| 動作温度 | Industrial, -40 C to +85 C | [DATA_NEEDED: industrial/commercial temperature range] |
| Configuration Memory | UV-erasable EPROM | — |
| Programming Method | External EPROM programmer (via programming hardware) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | — |
| Speed Grade | -1 (slowest grade in EPM5192 family) | — |
| Logic Element per Macrocell | 1 D flip-flop + AND/OR array | — |
| Usable Gates | — | 3750 |
| External Clock Inputs (GCLK) | — | 1 |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| Technology | — | CMOS EPROM (UV-erasable) |
| JEDEC Package Code | — | S-CQCC-J84 |
| Programming Interface | — | JTAG / Altera ByteBlaster |