EPM5192JI-2 vs EPM5192JI-1 比較
詳細な並列比較: EPM5192JI-2 メーカー: Altera および EPM5192JI-1 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192JI-2 | EPM5192JI-1 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $17.40 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CMOS UV-Erasable Programmable Logic Device (PLD / EPLD) |
| Macrocells | 192 | 192 |
| Usable Gates | 5000 | — |
| Dedicated Inputs | 12 | 7 |
| Flip-Flops | 192 | — |
| Speed Grade | -2 | -1 (slowest grade in EPM5192 family) |
| パッケージ | JLCC-68 (J-Lead Ceramic) | 84-pin JLCC (Windowed ceramic J-lead) |
| 動作温度 | 0C to +70C (commercial) | Industrial, -40 C to +85 C |
| Programming Technology | UV-Erasable EPROM | — |
| Architecture | Sum-of-products with Programmable Interconnect Array (PIA) | — |
| 電源電圧 | 5 V (typical) | — |
| Process Technology | CMOS EPROM | CMOS EPROM |
| 実装タイプ | Surface Mount | — |
| RoHS ステータス | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS compliance] |
| ライフサイクル状態 | Obsolete (legacy Altera MAX 5000 family) | — |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Propagation Delay (tPD) | — | 55 ns |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V (nominal 5 V) |
| Configuration Memory | — | UV-erasable EPROM |
| Programming Method | — | External EPROM programmer (via programming hardware) |
| Logic Element per Macrocell | — | 1 D flip-flop + AND/OR array |