EPM5192LC-2N vs EPM5192LC-45 比較
詳細な並列比較: EPM5192LC-2N メーカー: Altera および EPM5192LC-45 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192LC-2N | EPM5192LC-45 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $11.85 | $24.00 |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| Flip-Flops | 192 | — |
| Logic Elements | 192 macrocells (PAL/GAL-style AND-OR array) | 192 macrocells |
| Package Type | LC (ceramic J-leaded, windowed UV-erasable package family) | LCC (Leaded Ceramic Chip Carrier) with UV window |
| Speed Grade | -2 (tPD approximately 25 ns) | -45 (45 ns tPD) |
| Propagation Delay (typical) | 25 ns | — |
| 電源電圧 | 5 V (typical) | 5 V |
| Programmability | UV-erasable EPROM cell | — |
| 実装タイプ | Surface Mount (LC package) | Surface Mount (LCC) |
| 動作温度 | Commercial (0C to +70C) - inferred from speed-grade -2 designation | 0C to +70C (commercial) |
| RoHS ステータス | Compliant (per -N lead-free suffix) | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes (per -N suffix) | — |
| Architecture | Programmable Logic Array (PLA) with global PIA | — |
| Programming Interface | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) | — |
| Series | — | EPM5192 |
| Maximum Operating Frequency | — | 100 MHz |
| Pin-to-Pin Delay (tPD) | — | 45 ns |
| Dedicated Inputs | — | [DATA_NEEDED: dedicated input count] |
| Programmable I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| Configuration Memory | — | UV-erasable EPROM / OTP |
| Technology | — | EPROM-based CMOS |
| Package Code | — | LC |
| Datasheet Page Count | — | 52 pages |