EPM5192LC-35 vs EPM5192JC-1 比較
詳細な並列比較: EPM5192LC-35 メーカー: Altera および EPM5192JC-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192LC-35 | EPM5192JC-1 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $15.25 | $22.40 |
| Series | MAX 5000 | — |
| Family | MAX 5000 CPLD | MAX 5000 |
| Logic Elements / Macrocells | 192 macrocells | — |
| Pin-to-Pin Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| Programmable Type | UV-Erasable / OTP (EPROM-based) | — |
| Package Type | JLCC (J-Lead Ceramic Chip Carrier) | 84-pin Ceramic Quad Flat Pack (CQFP), windowed |
| 実装タイプ | Surface Mount | — |
| Logic Voltage | 5 V TTL-compatible I/O | — |
| 動作温度 | Commercial (0C to +70C) per LC suffix | 0 C to +70 C (commercial) |
| Programming Method | Altera legacy programmer (EPROM-based) | — |
| Architecture | LAB-based with Programmable Interconnect Array (PIA) | — |
| I/O Standard | TTL | TTL/CMOS 5 V compatible |
| RoHS ステータス | Non-compliant (ceramic hermetic package) | — |
| ライフサイクル状態 | Obsolete - last-time-buy stock only | — |
| Datasheet Document | Altera MAX 5000 family datasheet (per alldatasheet.com) | — |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Technology | — | CMOS, UV-Erasable / OTP |
| Macrocells | — | 192 |
| Usable Gates | — | 3750 |
| Propagation Delay (tPD) | — | 40 ns (speed grade -1) |
| Maximum Internal Frequency (fMAX) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| User I/O Pins | — | 84 |
| JEDEC Package Code | — | S-CQCC-J84 |
| Configuration Memory | — | UV-EPROM (erasable under UV lamp) |
| Programming Interface | — | Altera MAX programming interface (parallel, pre-JTAG for this family) |
| Process | — | CMOS EPROM |