EPM5192LC-35 vs EPM5192LC-1 比較
詳細な並列比較: EPM5192LC-35 メーカー: Altera および EPM5192LC-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192LC-35 | EPM5192LC-1 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $15.25 | $14.20 |
| Series | MAX 5000 | — |
| Family | MAX 5000 CPLD | MAX 5000 |
| Logic Elements / Macrocells | 192 macrocells | — |
| Pin-to-Pin Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | -1 |
| Programmable Type | UV-Erasable / OTP (EPROM-based) | — |
| Package Type | JLCC (J-Lead Ceramic Chip Carrier) | LDCC (Leaded Ceramic Chip Carrier), plastic windowless |
| 実装タイプ | Surface Mount | — |
| Logic Voltage | 5 V TTL-compatible I/O | — |
| 動作温度 | Commercial (0C to +70C) per LC suffix | 0C to +70C (commercial) |
| Programming Method | Altera legacy programmer (EPROM-based) | — |
| Architecture | LAB-based with Programmable Interconnect Array (PIA) | — |
| I/O Standard | TTL | — |
| RoHS ステータス | Non-compliant (ceramic hermetic package) | Non-compliant (ceramic LDCC with Pb-bearing terminations) |
| ライフサイクル状態 | Obsolete - last-time-buy stock only | — |
| Datasheet Document | Altera MAX 5000 family datasheet (per alldatasheet.com) | — |
| Device Type | — | EPLD / CPLD |
| Macrocells | — | 192 |
| Logic Gates | — | 3750 (typical usable) |
| Dedicated Inputs | — | 7 |
| User I/O | — | 64 |
| ピン数 | — | 84 |
| Propagation Delay | — | 25 ns |
| 最大クロック周波数 | — | 50 MHz |
| 電源電圧 | — | 5 V nominal (4.75 V to 5.25 V) |
| Technology | — | CMOS, UV-erasable / OTP EPROM cell |
| Programmable Memory | — | EPROM (one-time or UV-erasable) |