EPM7096LC84-10 vs EPM7096QC100-10 比較
詳細な並列比較: EPM7096LC84-10 メーカー: Intel および EPM7096QC100-10 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM7096QC100-10 - 96-Macrocell MAX 7000 CPLD, 10ns, PQFP-100 | Altera
EPM7096QC100-10 Obsolete仕様比較
| パラメータ | EPM7096LC84-10 | EPM7096QC100-10 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $5.10 | $7.10 |
| Family | MAX 7000 | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 96 | 96 |
| Logic Array Blocks (LABs) | 4 | — |
| Maximum User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 10 ns (-10 speed grade) | 10 ns |
| パッケージ | 84-PLCC (J-Lead) | 100-pin PQFP (R-PQFP-G100, 20×14 mm, 0.65 mm pitch) |
| Process Technology | EEPROM-based, 5.0 V low-power CMOS (L) | — |
| Supply Voltage (VCC) | 5.0 V nominal (4.75 V - 5.25 V) | 4.75 V to 5.25 V |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG | — |
| MultiVolt I/O | 2.5 V / 3.3 V / 5.0 V mixed-voltage interface | — |
| 動作温度範囲 | 0C to +70C (Commercial, 'C') | — |
| Configuration Memory | Non-volatile EEPROM (instant-on) | — |
| Programmable Interconnect | PIA (Programmable Interconnect Array) | — |
| 実装タイプ | Surface Mount (PLCC socket or SMT) | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Logic Array Blocks | — | 4 |
| User I/O Pins | — | 76 |
| Maximum Operating Frequency | — | 100 MHz |
| Technology | — | EEPROM-based CMOS |
| Programming Interface | — | ByteBlaster / parallel (JTAG ISP on MAX 7000S variants) |
| Boundary Scan | — | IEEE Std. 1149.1 (JTAG) on MAX 7000S |
| PCI Compliance | — | Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade) |
| 動作温度 | — | 0 °C to +70 °C (commercial) |