EPM7128ATC100-10 vs EPM7128AETI100-7N 比較
詳細な並列比較: EPM7128ATC100-10 メーカー: Altera および EPM7128AETI100-7N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM7128ATC100-10 - MAX 7000A CPLD, 128 Macrocells, 10ns TQFP-100 | Altera
EPM7128ATC100-10 ObsoleteAltera
EPM7128AETI100-7N - MAX 7000A CPLD 128 Macro 84 I/O | Intel/Altera
EPM7128AETI100-7N Obsolete仕様比較
| パラメータ | EPM7128ATC100-10 | EPM7128AETI100-7N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $4.95 | $28.50 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 7000A | MAX 7000A CPLD |
| Architecture | Multiple Array MatriX (MAX) | — |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Usable Gates | 2.5K | — |
| User I/O Pins | 68 | — |
| Pin-to-Pin Logic Delay | 4.5 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Speed Grade | -10 (10 ns) | — |
| Core Supply Voltage | 3.3 V | — |
| I/O Logic Level Support | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Program Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (JTAG IEEE 1149.1) |
| パッケージ | 100-pin TQFP (TC100) | 100-pin TQFP (14x14 mm) |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | 0C to +70C (commercial) | -40C to +85C (Industrial) |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | Compliant |
| Series | — | MAX 7000A |
| Macro Cells | — | 128 |
| Number of Usable Gates | — | 2,500 |
| Number of I/O | — | 84 |
| Number of Logic Array Blocks (LABs) | — | 8 |
| Propagation Delay (tPD max) | — | 7 ns |
| Maximum Operating Frequency (fCNT) | — | 129.9 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| I/O Bank Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) |
| Process Technology | — | CMOS EEPROM |