EPM7128BTC144-7 vs EPM7128AETC144-7N 比較
詳細な並列比較: EPM7128BTC144-7 メーカー: Altera および EPM7128AETC144-7N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM7128AETC144-7N - MAX 7000A CPLD, 128 Macros, 144-TQFP | Intel / Altera
EPM7128AETC144-7N ✓ 生産中仕様比較
| パラメータ | EPM7128BTC144-7 | EPM7128AETC144-7N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.85 | $39.82 |
| Family | MAX 7000B | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | — |
| Logic Array Blocks (LABs) | 8 | — |
| User I/O Pins | 100 (per 144-pin TQFP package) | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Maximum Counter Frequency (fCNT) | 126.6 MHz | — |
| Maximum Operating Frequency | 175 MHz (family typical) | 129.9 MHz |
| Supply Voltage (VCCINT) | 2.5 V | 3.3 V |
| I/O Bank Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multiVolt) | — |
| Configuration Memory | EEPROM (non-volatile, ISP) | — |
| Programmability | IEEE 1149.1 JTAG (ISP) | In-System Programmable (ISP) via JTAG |
| Operating Temperature (Commercial) | 0C to +90C | — |
| パッケージ | 144-pin TQFP | 144-pin TQFP |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | Yes |
| Logic Gates | — | 2500 (2.5K gates) |
| User I/Os | — | 36 (in 144-pin TQFP) |
| Pin-to-Pin Delay | — | 7.5 ns |
| Propagation Delay (tpd) | — | 7.5 ns |
| Process Technology | — | CMOS, EEPROM-based |
| Boundary-Scan Test | — | IEEE Std 1149.1 (JTAG) |
| 動作温度 | — | 0C to +70C (commercial) |
| Pin-Compatible With | — | MAX 7000S 5.0V family (144-pin TQFP) |