EPM7192EGM160-20 vs EPM7192EGC160-12 比較
詳細な並列比較: EPM7192EGM160-20 メーカー: Altera および EPM7192EGC160-12 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM7192EGM160-20 - 192-Macrocell MAX 7000 CPLD, 20ns PGA-160 | Altera
EPM7192EGM160-20 Obsolete仕様比較
| パラメータ | EPM7192EGM160-20 | EPM7192EGC160-12 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $15.60 | $10.85 |
| Family | MAX 7000 | — |
| Device Type | EE CMOS CPLD (Electrically Erasable) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 4 |
| Usable Gates | 600 to 5,000 | 3.75K |
| Maximum User I/O Pins | 120 | — |
| パッケージ | PGA-160 (160-pin Pin Grid Array) | 160-BPGA / PGA-160 (39.6 x 39.6 mm) |
| Speed Grade | -20 (20 ns pin-to-pin) | — |
| Pin-to-Pin Propagation Delay | 20 ns | — |
| Counter Frequency (max) | 175.4 MHz | — |
| I/O Standards | 3.3 V or 5 V configurable | — |
| Global Clock Inputs | 2 (GCLK1, GCLK2) | — |
| In-System Programming | Yes (JTAG IEEE 1149.1) | — |
| Program/Erase Endurance | 100 cycles (EEPROM) | — |
| 動作温度 | -40C to +125C (industrial) | 0 C to +90 C (Commercial) |
| Technology Node | CMOS, second-generation MAX architecture | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - not stated in provided web data] |
| Series | — | MAX 7000 |
| Device Family | — | MAX 7000E (EPM7192E) |
| User I/O Pins | — | 124 |
| Propagation Delay (tPD) | — | 12 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| Process Technology | — | CMOS, EEPROM-based |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| 実装タイプ | — | Through-Hole (Pin Grid Array, socketable) |