EPM7192EGM160-20 vs EPM7192EGI160-20 比較
詳細な並列比較: EPM7192EGM160-20 メーカー: Altera および EPM7192EGI160-20 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM7192EGM160-20 - 192-Macrocell MAX 7000 CPLD, 20ns PGA-160 | Altera
EPM7192EGM160-20 Obsolete仕様比較
| パラメータ | EPM7192EGM160-20 | EPM7192EGI160-20 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $15.60 | $264.10 |
| Family | MAX 7000 | MAX 7000 |
| Device Type | EE CMOS CPLD (Electrically Erasable) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Usable Gates | 600 to 5,000 | — |
| Maximum User I/O Pins | 120 | — |
| パッケージ | PGA-160 (160-pin Pin Grid Array) | 160-pin CPGA (Ceramic Pin Grid Array) |
| Speed Grade | -20 (20 ns pin-to-pin) | — |
| Pin-to-Pin Propagation Delay | 20 ns | — |
| Counter Frequency (max) | 175.4 MHz | — |
| I/O Standards | 3.3 V or 5 V configurable | — |
| Global Clock Inputs | 2 (GCLK1, GCLK2) | — |
| In-System Programming | Yes (JTAG IEEE 1149.1) | — |
| Program/Erase Endurance | 100 cycles (EEPROM) | — |
| 動作温度 | -40C to +125C (industrial) | — |
| Technology Node | CMOS, second-generation MAX architecture | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| Logic Array Blocks | — | 4 |
| User I/O Pins | — | 36 |
| Dedicated Inputs | — | 4 |
| Pin-to-Pin Delay (tpd) | — | 20 ns |
| Maximum Operating Frequency | — | 62.5 MHz |
| Supply Voltage (VCCINT) | — | 5.0 V |
| Program Memory Type | — | EEPROM |
| In-System Programmability | — | Yes (JTAG IEEE Std. 1149.1) |
| Operating Temperature Grade | — | Industrial (-40C to +85C) |
| Programming Interface | — | JTAG (ByteBlaster / USB-Blaster compatible) |