EPM7256SQC208-15 vs EPM7256SRC208-10 比較
詳細な並列比較: EPM7256SQC208-15 メーカー: Altera および EPM7256SRC208-10 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM7256SQC208-15 | EPM7256SRC208-10 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $3.65 | $27.20 |
| Family | MAX 7000S | MAX 7000S |
| Series | EPM7256 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 256 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 5000 | — |
| User I/O Pins | 164 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| 動作温度範囲 | 0 C to +70 C (Commercial) | — |
| パッケージ | 208-pin PQFP (28x28 mm) | 208-pin RQFP (BFQFP) exposed pad, 28x28 mm |
| 実装タイプ | Surface Mount | Surface Mount |
| Programmable Power Mode | Yes (per-macrocell turbo-bit) | — |
| JTAG (IEEE 1149.1) Boundary-Scan | Yes | — |
| In-System Programmability (ISP) | Yes | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| RoHS ステータス | Contains lead / RoHS non-compliant (per third-party listing) | [DATA_NEEDED: RoHS status] |
| Lead-Free Status | Contains lead | — |
| Number of Macrocells | — | 256 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| Number of Gates | — | 5000 |
| Number of User I/O Pins | — | 164 |
| Maximum Propagation Delay (tPD) | — | 10 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Supply Voltage (Internal) | — | 4.75 V to 5.25 V |
| Programmable Type | — | In System Programmable (ISP, JTAG) |
| Configuration Technology | — | EEPROM |
| 動作温度 | — | 0C to +70C (TA, commercial) |
| Terminal Form | — | Gull Wing |
| Package Shape | — | Square |
| Product Status | — | Obsolete |