EPM7256SQC208-7 vs EPM7256SRC208-10 比較
詳細な並列比較: EPM7256SQC208-7 メーカー: Altera および EPM7256SRC208-10 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM7256SQC208-7 | EPM7256SRC208-10 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $27.20 |
| Device Family | MAX 7000S (EPM7256S) | — |
| Macrocells | 256 | — |
| Usable Gates | 5,000 | — |
| User I/O Pins | 164 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Operating Frequency (fMAX) | 128.2 MHz | — |
| Supply Voltage (VCC) | 5.0 V | — |
| Configuration Technology | EEPROM (non-volatile) | EEPROM |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| パッケージ | 208-pin PQFP (28 x 28 mm, 0.5 mm pitch) | 208-pin RQFP (BFQFP) exposed pad, 28x28 mm |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度範囲 | Commercial (0C to +70C) | — |
| Minimum DC Input Voltage | -0.5 V | — |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns | — |
| Speed Grade | -7 (7.5 ns) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| MSLレベル | [DATA_NEEDED: MSL level] | — |
| Logic Levels | 5.0 V CMOS/TTL compatible | — |
| Family | — | MAX 7000S |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | — | 256 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| Number of Gates | — | 5000 |
| Number of User I/O Pins | — | 164 |
| Maximum Propagation Delay (tPD) | — | 10 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Supply Voltage (Internal) | — | 4.75 V to 5.25 V |
| Programmable Type | — | In System Programmable (ISP, JTAG) |
| 動作温度 | — | 0C to +70C (TA, commercial) |
| Terminal Form | — | Gull Wing |
| Package Shape | — | Square |
| Product Status | — | Obsolete |