EPM9320RC208-15 vs EPM9320RI208-20N 比較
詳細な並列比較: EPM9320RC208-15 メーカー: Altera および EPM9320RI208-20N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9320RC208-15 | EPM9320RI208-20N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $0.00 |
| Device Family | MAX 9000 | MAX 9000 (EPM9320) |
| Macro Cells | 320 | — |
| Usable Gates | 6,000 | — |
| Pin-to-Pin Propagation Delay | 15 ns (speed grade -15) | — |
| 最大クロック周波数 | 117.6 MHz | — |
| 電源電圧 | 5.0 V | — |
| Configuration Technology | EEPROM-based (non-volatile) | — |
| In-System Programmability | Yes (ISP via JTAG) | Yes, 5.0 V ISP via JTAG |
| JTAG Interface | IEEE Std. 1149.1 | IEEE Std. 1149.1 compliant |
| パッケージ | 208-pin RQFP (Power QFP) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Package Type | 208-BFQFP Exposed Pad | — |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | [DATA_NEEDED: operating temperature range] | — |
| Number of I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Logic Array Blocks | [DATA_NEEDED: LAB count] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| ライフサイクル状態 | Obsolete (PDN0706, 2007) | — |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | — | 320 |
| Flip-Flops | — | 484 |
| Propagation Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V or 5 V configurable |
| Package Lead Pitch | — | 0.500 mm |
| Number of Terminals | — | 208 |
| 動作温度範囲 | — | -40C to +85C (Industrial) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Dedicated Input Pins | — | 4 (low-skew global distribution) |
| Minimum DC Input on I/O Pins | — | -0.5 V |
| Minimum DC Input on Dedicated Inputs | — | -0.3 V |
| Input Undershoot/ Overshoot | — | -2.0 V / 7.0 V for <20 ns (no-load) |