EPM9400LC84-20 vs EPM9560ELI84-20 比較
詳細な並列比較: EPM9400LC84-20 メーカー: Altera および EPM9560ELI84-20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM9560ELI84-20 - MAX 9000 6k-Gate EPLD, 84-Pin PLCC | Intel / Altera
EPM9560ELI84-20 Obsolete仕様比較
| パラメータ | EPM9400LC84-20 | EPM9560ELI84-20 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $38.50 | $19.50 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Architecture | Multiple Array Matrix (MAX), 3rd generation, EEPROM-based | Multiple Array MatriX (MAX) - EEPROM-based |
| Macrocells | 400 | 560 |
| Usable Gates | 8,000 (6,000 to 12,000 typical range) | 6,000 |
| Flip-Flops | 580 | 212 |
| Maximum User I/O | 55 | 212 (package-dependent) |
| Pin-to-Pin Propagation Delay | 20 ns (speed grade -20) | 20 ns |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (configurable) | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| パッケージ | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| 動作温度 | Commercial (0C to +70C) - assumed from -20 speed grade | -40C to +85C (industrial) |
| 実装タイプ | Surface Mount (PLCC socket or SMT land pattern) | Through-Hole / Socket |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Logic Array Blocks (LABs) | — | 16 |
| Speed Grade | — | -20 |
| Supply Voltage (VCC) | — | 5.0 V |
| In-System Programmability | — | 5.0 V ISP via IEEE 1149.1 JTAG |
| I/O Standards | — | 5.0 V, 3.3 V, 2.5 V (multiVolt I/O) |