EPM9400RC208-20 vs EPM9560RI208-15N 比較
詳細な並列比較: EPM9400RC208-20 メーカー: Altera および EPM9560RI208-15N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9400RC208-20 | EPM9560RI208-15N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $60.49 | $19.45 |
| Family | MAX 9000 | — |
| Programmable Type | In System Programmable (ISP) | — |
| Macro Cells | 400 | — |
| Usable Gates | 8,000 | — |
| Pin-to-Pin Propagation Delay | 20 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Supply Voltage (Internal) | 4.75 V to 5.25 V | — |
| Configuration Technology | EEPROM-based (non-volatile) | — |
| JTAG Interface | IEEE Std. 1149.1 | — |
| パッケージ | 208-pin RQFP (28x28 mm) | 208-pin RQFP (Ruggedized Quad Flat Pack) |
| Supplier Device Package | 208-RQFP | — |
| 実装タイプ | Surface Mount | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0C to 70C (Commercial) |
| Number of I/O Pins | [DATA_NEEDED: user I/O count] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| MSLレベル | [DATA_NEEDED: moisture sensitivity level] | — |
| Speed Grade | -20 (20 ns) | -15 |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Device Family | — | MAX 9000 |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Architecture | — | Multiple Array MatriX (MAX), 3rd generation |
| Configuration Memory | — | CMOS EEPROM, in-system programmable |
| Total Pins | — | 356 (per third-party catalog; see _validation_note) |
| Package Pin Count | — | 208 |
| Terminal Form | — | Gull Wing |
| Package Code | — | HFQFP |
| User I/Os | — | 216 (per DigiChip specification; see _validation_note) |
| Maximum Internal Frequency | — | 145 MHz |
| Propagation Delay (tPD) | — | 11.4 ns (15 ns speed grade) |
| 電源電圧 | — | 5.0 V |
| Temperature Grade | — | Industrial (per Vyrian/Partstack listings) |
| Logic Family | — | CMOS |
| Programming Interface | — | IEEE 1149.1 JTAG, 5.0-V in-system |