EPM9560ARI240-10 vs EPM9560ARI208-10N 比較
詳細な並列比較: EPM9560ARI240-10 メーカー: Altera および EPM9560ARI208-10N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM9560ARI208-10N - MAX 9000 CPLD 12K Gates 560 Macrocells | Altera
EPM9560ARI208-10N Obsolete仕様比較
| パラメータ | EPM9560ARI240-10 | EPM9560ARI208-10N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $22.10 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 12,000 | 12,000 |
| Macro Cells | 560 | — |
| User I/O Pins | 191 | — |
| パッケージ | 240-pin RQFP (PowerQuad Flat Pack) | 208-pin RQFP (Plastic) |
| Pin-to-Pin Propagation Delay | 10 ns | — |
| Internal Frequency | 144.9 MHz | — |
| 電源電圧 | 5.0 V | 5.0 V |
| Technology | CMOS, EEPROM-based configuration | — |
| 動作温度範囲 | -40 C to +85 C (industrial) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile, instant-on) | — |
| Logic Architecture | Multiple Array MatriX (MAX) with global interconnect array | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | — |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL level] | — |
| Number of Terminals | 240 | — |
| Terminal Form | Gull Wing | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 560 |
| Logic Array Blocks (LABs) | — | 35 |
| Maximum User I/O Pins | — | 212 |
| Flip-Flops | — | 484 |
| Propagation Delay (tPD1) | — | 10 ns |
| Clock-to-Output (tCO) | — | 4.5 ns |
| Setup Time (tSU) | — | 3.0 ns |
| Maximum Counter Frequency (fCNT) | — | 144.9 MHz |
| Logic Family | — | CMOS EEPROM |
| Programming Interface | — | JTAG (IEEE 1149.1) - In-System Programmable |
| 動作温度 | — | 0 C to 70 C (Commercial) |