EPM9560GC280-15 vs EPM9560ARC304-10F 比較
詳細な並列比較: EPM9560GC280-15 メーカー: Altera および EPM9560ARC304-10F メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 Obsolete仕様比較
| パラメータ | EPM9560GC280-15 | EPM9560ARC304-10F |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $115.00 | $0.00 |
| Family | MAX 9000 | — |
| Device Type | EE PLD (CMOS EEPROM-based CPLD) | — |
| Macro Cells | 560 | — |
| Typical Gates | 12,000 | — |
| Maximum Operating Frequency | 117.6 MHz | — |
| Propagation Delay (tpd) | 15 ns (speed grade -15) | — |
| Propagation Delay (alternate datasheet figure) | 16.6 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Package Type | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | — |
| 実装タイプ | Through-Hole | Surface Mount |
| Programmability | In-System Programmable (ISP) via JTAG IEEE 1149.1 | — |
| Technology | CMOS EEPROM, 0.5 um process (MAX third-gen) | — |
| Architecture | Multiple Array MatriX (MAX) | — |
| RoHS ステータス | Non-compliant (ceramic CPGA, contains lead) | RoHS |
| ライフサイクル状態 | Obsolete (legacy Altera MAX 9000 family) | — |
| Device Family | — | MAX 9000A |
| Programmable Type | — | In System Programmable (ISP) |
| Number of Macrocells | — | 560 |
| Number of Logic Elements/Blocks | — | 35 LABs |
| Number of Gates | — | 12000 |
| Number of I/O | — | 216 |
| Maximum Delay Time (tPD) | — | 10 ns |
| Supply Voltage (Internal) | — | 4.75 V to 5.25 V |
| 動作温度 | — | 0 C to +70 C (commercial) |
| パッケージ | — | 304-pin RQFP (PowerQuad II) |
| Package Code | — | FQFP |
| Terminal Form | — | Gull Wing |
| Package Shape | — | Square |
| Configuration Memory | — | EEPROM (non-volatile) |
| JTAG Support | — | IEEE 1149.1 (ISP) |
| Speed Grade | — | -10 (10 ns) |