EPM9560GC280-15 vs EPM9560GM280-15 比較
詳細な並列比較: EPM9560GC280-15 メーカー: Altera および EPM9560GM280-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 Obsolete仕様比較
| パラメータ | EPM9560GC280-15 | EPM9560GM280-15 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $115.00 | $110.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE PLD (CMOS EEPROM-based CPLD) | EE PLD (EEPROM-based) |
| Macro Cells | 560 | — |
| Typical Gates | 12,000 | — |
| Maximum Operating Frequency | 117.6 MHz | — |
| Propagation Delay (tpd) | 15 ns (speed grade -15) | — |
| Propagation Delay (alternate datasheet figure) | 16.6 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| Package Type | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | — |
| 実装タイプ | Through-Hole | — |
| Programmability | In-System Programmable (ISP) via JTAG IEEE 1149.1 | — |
| Technology | CMOS EEPROM, 0.5 um process (MAX third-gen) | — |
| Architecture | Multiple Array MatriX (MAX) | — |
| RoHS ステータス | Non-compliant (ceramic CPGA, contains lead) | ROHS3 Compliant |
| ライフサイクル状態 | Obsolete (legacy Altera MAX 9000 family) | — |
| Macrocells | — | 560 |
| Flip-Flops | — | 772 |
| User I/O | — | 216 |
| Logic Array Blocks (LABs) | — | 35 (16 macrocells each) |
| Supply Voltage (Nominal) | — | 5.0 V |
| Supply Voltage (Max) | — | 5.5 V |
| I/O Logic Level Support | — | 3.3 V or 5 V |
| Pin-to-Pin Delay (tPD) | — | 15 ns (speed grade -15) |
| パッケージ | — | FineLine BGA-280 (GM) |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (5V ISP via JTAG IEEE 1149.1) |
| 動作温度 | — | -40C to +85C (industrial) |
| MSLレベル | — | 3 (168 Hours) |