EPM9560GC280-15N vs EPM9320GC280-15 比較
詳細な並列比較: EPM9560GC280-15N メーカー: Intel および EPM9320GC280-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM9320GC280-15 - 320-Macrocell MAX 9000 CPLD, 15ns, CPGA-280 | Altera
EPM9320GC280-15 Obsolete仕様比較
| パラメータ | EPM9560GC280-15N | EPM9320GC280-15 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $125.00 | $92.50 |
| Device Family | MAX 9000 | — |
| Product Type | EE PLD / CPLD | — |
| Macrocell Count | 560 | — |
| Usable Gates | 12,000 (typical) | 6,000 |
| Propagation Delay (tPD) | 16.6 ns | — |
| 最大クロック周波数 | 117.6 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Maximum Supply Voltage | 5.25 V | — |
| Logic Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (5.0-V ISP via JTAG) | — |
| Boundary-Scan (JTAG) | IEEE Std. 1149.1 compliant | — |
| パッケージ | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | 280-pin Ceramic Pin Grid Array (CPGA-280) |
| Package Code | PGA / CPGA280 | — |
| Terminal Form | PIN/PEG | — |
| Operating Temperature Grade | Commercial | — |
| Architecture | Multiple Array MatriX (MAX) 3rd generation | CMOS EEPROM-based, Multiple Array MatriX (MAX) |
| Family | — | MAX 9000 (EPM9320) |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Macrocells | — | 320 |
| Logic Array Blocks (LABs) | — | 20 (16 macrocells per LAB) |
| Pin-to-Pin Propagation Delay | — | 15 ns |
| Maximum Internal Frequency | — | 117.6 MHz |
| Maximum User I/O Pins | — | 164 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| I/O Voltage Levels | — | 3.3 V or 5 V (configurable) |
| Programmability | — | 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG |
| 実装タイプ | — | Through-hole (PGA socket) |
| 動作温度 | — | 0 C to +70 C (commercial) |
| MSLレベル | — | 3 (168 hours) |
| RoHS ステータス | — | ROHS3 compliant (per fpgalink listing) |
| Technology Node | — | CMOS EEPROM, third-generation MAX |