EPM9560GC280-20 vs EPM9560GC280-15 比較
詳細な並列比較: EPM9560GC280-20 メーカー: Altera および EPM9560GC280-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 Obsolete仕様比較
| パラメータ | EPM9560GC280-20 | EPM9560GC280-15 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $360.00 | $115.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EE PLD (CMOS EEPROM-based CPLD) |
| Usable Gates | 12,000 | — |
| Macrocells | 560 | — |
| Maximum User I/O | 212 | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| Counter Frequency (max) | 100 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| I/O Voltage | 3.3 V or 5.0 V configurable | — |
| Process Technology | CMOS EEPROM | — |
| パッケージ | 280-pin CPGA (Ceramic Pin Grid Array) | — |
| 動作温度 | [DATA_NEEDED: commercial/industrial/military grade] | — |
| In-System Programming | Yes, via IEEE 1149.1 JTAG | — |
| 実装タイプ | Through-Hole (CPGA socket) | Through-Hole |
| RoHS ステータス | [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] | Non-compliant (ceramic CPGA, contains lead) |
| Macro Cells | — | 560 |
| Typical Gates | — | 12,000 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (tpd) | — | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | — | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Package Type | — | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Programmability | — | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Technology | — | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Architecture | — | Multiple Array MatriX (MAX) |
| ライフサイクル状態 | — | Obsolete (legacy Altera MAX 9000 family) |