EPM9560GI280-20 vs EPM9560GC280-15N 比較
詳細な並列比較: EPM9560GI280-20 メーカー: Intel および EPM9560GC280-15N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9560GI280-20 | EPM9560GC280-15N |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $162.50 | $125.00 |
| Device Family | MAX 9000 | MAX 9000 |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) 3rd generation |
| Technology Node | 5.0 V CMOS EEPROM | — |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 28 (16 macrocells each) | — |
| Usable Gates | 12,000 | 12,000 (typical) |
| Maximum User I/O Pins | 216 | — |
| Flip-Flops | 772 | — |
| Pin-to-Pin Delay (Speed Grade) | 20 ns | — |
| Supply Voltage (VCC) | 5.0 V | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | Yes (5.0-V ISP via JTAG) |
| Programming Technology | EEPROM (non-volatile) | — |
| パッケージ | 280-pin PGA (PIN/PEG, square) | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Terminal Form | PIN/PEG (through-hole PGA) | PIN/PEG |
| Package Code | PGA | PGA / CPGA280 |
| Temperature Grade | Industrial | — |
| I/O Pin DC Input Range | -0.5 V to VCC + 0.5 V | — |
| Dedicated-Input Pin DC Input Range | -0.3 V to VCC + 0.3 V | — |
| I/O Transient Envelope (no-load, <20 ns) | -2.0 V undershoot to 7.0 V overshoot | — |
| VCC Ramp Requirement | Monotonic rise | — |
| Development Tool | Altera MAX+PLUS II | — |
| Supported HDLs | VHDL, Verilog HDL, AHDL | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status for GI PGA package] | — |
| Product Type | — | EE PLD / CPLD |
| Macrocell Count | — | 560 |
| Propagation Delay (tPD) | — | 16.6 ns |
| 最大クロック周波数 | — | 117.6 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Maximum Supply Voltage | — | 5.25 V |
| Logic Technology | — | CMOS EEPROM |
| Boundary-Scan (JTAG) | — | IEEE Std. 1149.1 compliant |
| Operating Temperature Grade | — | Commercial |