LFE5UM5G-85F8BG554I vs LFE5UM5G-85F-8BG554I 比較
詳細な並列比較: LFE5UM5G-85F8BG554I メーカー: Lattice Semiconductor および LFE5UM5G-85F-8BG554I メーカー: Lattice Semiconductor。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Lattice Semiconductor
LFE5UM5G-85F8BG554I - 84K LUT, 5G SERDES ECP5 FPGA | Lattice
LFE5UM5G-85F8BG554I ✓ 生産中Lattice Semiconductor
LFE5UM5G-85F-8BG554I - 84K LUT ECP5-5G FPGA, 5G SERDES, BG554 | Lattice
LFE5UM5G-85F-8BG554I ✓ 生産中仕様比較
| パラメータ | LFE5UM5G-85F8BG554I | LFE5UM5G-85F-8BG554I |
|---|---|---|
| ブランド | Lattice Semiconductor | Lattice Semiconductor |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $99.60 | $198.00 |
| Product Family | ECP5-5G | — |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Logic Elements / LUT4 | 83,600 (84,000 nominal) | — |
| Embedded Block RAM (EBR) | 3,744 Kbit (3,833,856 bits) | — |
| Distributed RAM (LUT-based) | [DATA_NEEDED: distributed RAM in Kbit] | — |
| DSP / 18x18 Multipliers | 156 | — |
| SERDES Channels | 4 (5 Gbps multi-protocol) | — |
| SERDES Protocols | PCIe Gen1/Gen2, SGMII, CPRI, JESD204B, 5G multi-protocol | — |
| User I/O Count (this package) | 259 | — |
| Core Voltage | 1.2 V | — |
| パッケージ | 554-FBGA (caBGA) | 554-ball caBGA (BG554) |
| 動作温度 | -40C to +100C (Industrial) | -40C to +100C (Industrial, I suffix) |
| 実装タイプ | Surface Mount | Surface Mount |
| 湿気感度レベル（MSL） | 3 | — |
| Peak Reflow Temperature | 260C (30 s max, JESD-609 e1) | 260 C (max 30 s) |
| Terminal Finish | Tin Silver Copper (SnAgCu) | Tin-Silver-Copper (e1, JESD-609) |
| Configuration | SPI, JTAG, sysCONFIG, dual-boot, multi-boot, TransFR | — |
| Boundary Scan | IEEE 1149.1 compliant | — |
| Design Software | Lattice Diamond / Lattice Radiant | Lattice Diamond |
| RoHS ステータス | Compliant (per Lattice product page) | — |
| Family | — | ECP5-5G (LatticeECP5-5G) |
| Logic Elements / Cells | — | 84,000 (83.6K LUTs) |
| Number of LABs/CLBs | — | 21,000 |
| Total Block RAM Bits | — | 3,833,856 (3,744 Kb) |
| Number of User I/O | — | 259 |
| Number of 5G SERDES Channels | — | [DATA_NEEDED: SERDES channel count for BG554 package] |
| Core Voltage (VCC) | — | 1.1 V |
| Auxiliary Voltage (VCCAUX) | — | 1.2 V |
| Process Technology | — | 40 nm CMOS |
| Speed Grade | — | -8 |
| MSLレベル | — | 3 |
| Halogen-Free / RoHS | — | Halogen-Free (Green), RoHS compliant |
| Configuration Interface | — | JTAG (IEEE 1149.1), SPI; supports Dual-Boot, Multi-Boot, TransFR |