LTC2150CUJ-14 vs LTC2155CUP-14 比較
詳細な並列比較: LTC2150CUJ-14 メーカー: Analog Devices および LTC2155CUP-14 メーカー: Analog Devices。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Analog Devices
LTC2150CUJ-14 - 14-Bit 170Msps 1.8V ADC DDR LVDS | Analog Devices
LTC2150CUJ-14 ✓ 生産中
仕様比較
| パラメータ | LTC2150CUJ-14 | LTC2155CUP-14 |
|---|---|---|
| ブランド | Analog Devices | Analog Devices |
| カテゴリ | ADC/DAC | ADC/DAC |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $41.58 | $78.95 |
| 分解能 | 14 bit | 14 bit |
| Number of Channels | 1 | 2 (dual, simultaneous sampling) |
| Sample Rate | 170 Msps | — |
| Architecture | Pipelined | Pipelined |
| Analog Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) | 1.7 V to 1.9 V (1.8 V nominal) |
| Digital Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) | 1.7 V to 1.9 V (1.8 V nominal) |
| INL (typical) | ±0.85 LSB | — |
| DNL (typical) | ±0.25 LSB | — |
| Transition Noise | 1.82 LSBRMS | — |
| Missing Codes | None over temperature | — |
| Full-Power Sample/Hold Bandwidth | 1.25 GHz | — |
| Digital Output Interface | DDR LVDS | — |
| Encode Clock Inputs | Differential ENC+/ENC- (sine, PECL, LVDS, TTL, CMOS) | — |
| Clock Duty-Cycle Stabilizer | Optional (selectable) | — |
| Configuration Interface | Serial SPI port | — |
| Latency | 5 clock cycles | — |
| Power-Saving Modes | Sleep and Nap modes | — |
| パッケージ | 40-QFN (6 mm × 6 mm) with exposed pad | 64-QFN (9x9 mm) with exposed pad |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | Compliant (Pb-free #PBF suffix) | Compliant (PBF suffix indicates Pb-free) |
| サンプリングレート | — | 170 MSPS per channel |
| Input Type | — | Differential |
| 出力タイプ | — | Parallel CMOS / DDR LVDS selectable |
| Analog Input Bandwidth | — | 1.4 GHz |
| SNR | — | 70.1 dB (at 100 MHz input, per family datasheet) |
| SFDR | — | 88 dB (per family datasheet) |
| Power Consumption | — | [DATA_NEEDED: total power per pair at 170 Msps] |
| 動作温度範囲 | — | 0C to +70C (C suffix = commercial) |
| MSLレベル | — | [DATA_NEEDED] |