P5010NXN1TNB vs P5010NXN1TNB557 比較
詳細な並列比較: P5010NXN1TNB メーカー: NXP Semiconductors および P5010NXN1TNB557 メーカー: NXP Semiconductors。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
NXP Semiconductors
P5010NXN1TNB - QorIQ P5 SoC, e5500 1-Core 2GHz, 1295-FCBGA | NXP
P5010NXN1TNB ✓ 生産中NXP Semiconductors
P5010NXN1TNB557 - QorIQ P5 e5500 64-bit 2.0GHz MPU, 1295-FCPBGA | NXP
P5010NXN1TNB557 ✓ 生産中仕様比較
| パラメータ | P5010NXN1TNB | P5010NXN1TNB557 |
|---|---|---|
| ブランド | NXP Semiconductors | NXP Semiconductors |
| カテゴリ | Microcontrollers | Microcontrollers |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $296.54 | $28.80 |
| Manufacturer | NXP Semiconductors | — |
| Series | QorIQ P5 | — |
| Core Architecture | Power Architecture e5500 | — |
| Number of Cores | 1 | 1 |
| データバス幅 | 64-bit | — |
| Address Bus Width | 16-bit (per partstack MPN detail) | — |
| Maximum Core Frequency | 2.0 GHz | 2.0 GHz |
| L1 Cache (per core) | 32 KB I-cache + 32 KB D-cache | — |
| L2 Cache | 512 KB shared | Integrated (per QorIQ P5 family) |
| Memory Controller | 64-bit DDR3/DDR3L with ECC, up to 1866 MT/s | DDR3 with ECC (per QorIQ P5 family) |
| Ethernet | 10/100/1000 MACs (RGMII/SGMII), IEEE 1588 | — |
| PCI Express | 2 x PCIe Gen 2.0 controllers | — |
| Serial RapidIO | RapidIO 2.0 port | — |
| Security Engine | Integrated SEC 4.x | SEC 4.0+ (cryptographic accelerator) |
| USB | USB 2.0 | — |
| TDM/HDLC | 8 channels | — |
| 動作温度 | -40C to +105C (NXN extended) | -40C to +105C (industrial, typical QorIQ) |
| Core Voltage | 0.9 V (per QorIQ platform) | — |
| パッケージ | 1295-ball FCBGA (FC-PBGA), 37.5 x 37.5 mm | 1295-FCPBGA (37.5 x 37.5 mm) |
| 実装タイプ | Surface Mount | Surface Mount |
| Encryption Restricted | No (NXN = non-restricted; TSN suffix required for restricted) | — |
| Process Technology | [DATA_NEEDED: process technology node] | — |
| Thermal Resistance Theta-JA | [DATA_NEEDED: theta_JA value] | — |
| Architecture | — | PowerPC e5500 |
| Core | — | QorIQ P5, 64-bit |
| High-Speed Serial Interfaces | — | Multiple SerDes lanes for 1G/10G Ethernet |
| Ethernet MACs | — | Multi-gigabit (per family datasheet) |
| Instruction Set | — | Power Architecture 64-bit |
| RoHS ステータス | — | Compliant |
| MSLレベル | — | [DATA_NEEDED: MSL Level] |