RTAX1000S-1CGS624V vs RTAX2000S-1CGS624EV 比較
詳細な並列比較: RTAX1000S-1CGS624V メーカー: Microchip Technology および RTAX2000S-1CGS624EV メーカー: Microchip Technology。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Microchip Technology
RTAX1000S-1CGS624V - 1M-Gate Rad-Tolerant FPGA | Microchip
RTAX1000S-1CGS624V ✓ 生産中Microchip Technology
RTAX2000S-1CGS624EV - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000S-1CGS624EV ✓ 生産中仕様比較
| パラメータ | RTAX1000S-1CGS624V | RTAX2000S-1CGS624EV |
|---|---|---|
| ブランド | Microchip Technology | Microchip Technology |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $3,600.00 |
| Equivalent System Gates | 1,000,000 | — |
| Dedicated Logic Cells | 18144 | — |
| Cluster Logic Blocks (CLBs) | 12096 | — |
| Technology | CMOS, antifuse-based | — |
| Core Supply Voltage | 1.5 V | 1.5 V nominal (1.425 V to 1.575 V) |
| Family | RTAX-S (Radiation-Tolerant) | — |
| Programming Type | One-Time Programmable (antifuse) | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| パッケージ | CGS624 (624-ball ceramic column grid array) | 624-pin Ceramic Column Grid Array (CGA-624 / CCGA624) |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | -55C to +125C | -55C to +125C |
| Radiation Tolerance | Designed for space-flight radiation environments | — |
| Live at Power-Up | Yes (no external configuration device) | — |
| System Features | Segmentable clocks, chip-wide highway routing | — |
| Application Domain | Space-flight systems | — |
| RoHS ステータス | [DATA_NEEDED: RoHS Status] | [DATA_NEEDED: RoHS status] |
| I/O Standard Support | [DATA_NEEDED: I/O standards] | — |
| System Gates | — | 2,000,000 |
| Logic Cells (CLBs) | — | 21504 |
| Total Cells | — | 32256 |
| Additional ASIC Equivalent Gates | — | 250000 |
| Process Technology | — | 0.15 um CMOS |
| Maximum Frequency | — | 649 MHz |
| Logic Family | — | CMOS |
| SEU Immunity | — | SEU-hardened registers, immune to single-event upsets to specified LET threshold |
| SEU Rate | — | < 10-10 errors/bit-day |
| Configuration | — | One-time programmable anti-fuse, live at power-up, single chip |
| Product Family | — | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs |
| Thermal Resistance Basis | — | JEDEC JESD51 simulation conditions (per datasheet) |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |
| Maximum User I/O | — | [DATA_NEEDED: user I/O count] |