RTAX4000SL-LG1272V vs RTAX4000SL-LG1272E 比較
詳細な並列比較: RTAX4000SL-LG1272V メーカー: Microchip Technology および RTAX4000SL-LG1272E メーカー: Microchip Technology。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Microchip Technology
RTAX4000SL-LG1272V - 4M-Gate Rad-Tolerant FPGA | Microchip
RTAX4000SL-LG1272V ✓ 生産中Microchip Technology
RTAX4000SL-LG1272E - 4M-Gate Rad-Tolerant FPGA LGA-1272 | Microchip
RTAX4000SL-LG1272E ✓ 生産中仕様比較
| パラメータ | RTAX4000SL-LG1272V | RTAX4000SL-LG1272E |
|---|---|---|
| ブランド | Microchip Technology | Microchip Technology |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $0.00 |
| Logic Cells | 60480 | 60,480 |
| CLBs | 40320 | — |
| Equivalent System Gates | 4000000 | — |
| Family | RTAX-S/SL and RTAX-DSP | RTAX-SL Radiation-Tolerant FPGA |
| Programming Technology | Antifuse (one-time programmable) | — |
| Radiation Tolerance | Radiation-tolerant, space-flight grade | Radiation-tolerant (spaceflight class) |
| Power-Up Mode | Live at power-up (LAPU) | — |
| Form Factor | True single-chip | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | — |
| Clocking | Segmentable clocks | — |
| Routing | Chip-wide highway routing, carry logic | — |
| Base Architecture | Microsemi Axcelerator commercial family | — |
| パッケージ | 1272-pin ceramic LG (CGA) package | 1272-Pin LGA (Ceramic Column) |
| 実装タイプ | Surface Mount | Surface Mount |
| Application Domain | Space-flight systems | Space-flight systems |
| RoHS ステータス | [DATA_NEEDED: RoHS Status] | — |
| 動作温度 | [DATA_NEEDED: Operating Temperature] | [DATA_NEEDED: operating temperature range] |
| Core Voltage | [DATA_NEEDED: Core Voltage] | — |
| Maximum User I/O | [DATA_NEEDED: Maximum User I/O] | — |
| Embedded SRAM Bits | [DATA_NEEDED: Embedded SRAM Bits] | — |
| Equivalent Gates | — | 4,000,000 |
| CLBs (Logic Modules) | — | 40,320 |
| Process Technology | — | 0.15 um CMOS |
| Core Supply Voltage | — | 1.5 V (1.425 V to 1.575 V) |
| Programmable Technology | — | Antifuse |
| Configuration | — | Live at power-up, single-chip |
| Packaging | — | Box |
| Max Combinatorial Delay per CLB | — | [DATA_NEEDED: max combinatorial delay for base speed grade] |
| I/O Standards | — | [DATA_NEEDED: supported I/O standards] |