S912XDG128F2MALR vs MC9S12DG128VFUE 比較
詳細な並列比較: S912XDG128F2MALR メーカー: NXP Semiconductors および MC9S12DG128VFUE メーカー: NXP Semiconductors。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
NXP Semiconductors
S912XDG128F2MALR - 16-bit S12X MCU 128KB Flash 80MHz | NXP
S912XDG128F2MALR Obsolete仕様比較
| パラメータ | S912XDG128F2MALR | MC9S12DG128VFUE |
|---|---|---|
| ブランド | NXP Semiconductors | NXP Semiconductors |
| カテゴリ | Microcontrollers | Microcontrollers |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価(USD) | $10.40 | $0.00 |
| Core | HCS12X (S12X) | — |
| CPU Architecture | 16-bit | — |
| Maximum CPU Frequency | 80 MHz | — |
| Program Flash | 128 KB (128K x 8) | — |
| RAM | [DATA_NEEDED: RAM size] | — |
| Data EEPROM | [DATA_NEEDED: EEPROM size] | — |
| パッケージ | 112-LQFP (20 x 20 mm) | 80-QFP (14x14 mm), LQFP-80 |
| 動作温度 | -40 °C to +125 °C | [DATA_NEEDED: operating temperature range] |
| Automotive Qualification | Yes (AEC-Q100) | — |
| 電源電圧 | [DATA_NEEDED: VDD range] | 2.35 V to 2.75 V (core); 5 V I/O per distributor data |
| ADC | 10-bit (per family) | — |
| CAN Modules | 1 x CAN 2.0 (per family) | — |
| Serial Interfaces | SCI / SPI / I2C (per family) | — |
| XGATE Co-processor | Yes (per family) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | Compliant (per NXP product page) | [DATA_NEEDED: RoHS status] |
| MSLレベル | [DATA_NEEDED: MSL rating] | — |
| Instruction Set Compatibility | Upward compatible with HCS12 | — |
| Core Processor | — | HCS12 (16-bit CISC) |
| Core Size | — | 16-bit |
| Maximum Clock Speed | — | 25 MHz |
| Program Memory Size | — | 128KB (128K x 8) |
| Program Memory Type | — | FLASH |
| RAM Size | — | 8K x 8 |
| EEPROM Size | — | 2K x 8 |
| Connectivity | — | CANbus, I2C, SCI, SPI |
| Peripherals | — | PWM, WDT, LVD, POR |
| Number of I/O | — | 59 |
| ADC Resolution | — | 10-bit |
| Number of ADC Channels | — | 16 (two 8-channel ADCs) |
| データバス幅 | — | 16 bit |
| Qualification | — | Automotive AEC-Q100 (per Arrow listing) |
| ライフサイクル状態 | — | NRND (Not Recommended for New Designs) per NXP |