74LV4053D,118 - Triple SPDT Analog Switch, 2:1 MUX, SO-16 | Nexperia
部品番号: 74LV4053D,118 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $0.62 | $0.62 |
| 10 | $0.55 | $5.50 |
| 100 | $0.41 | $41.00 |
| 500 | $0.33 | $165.00 |
| 1,000 | $0.28 | $280.00 |
74LV4053D,118 概要
An analog switch IC (also called a CMOS transmission gate or bilateral switch) is a solid-state device that uses MOSFET pairs to route analog or digital signals between multiple nodes without mechanical contacts. Analog switches sit at the boundary between the analog signal chain and the digital control logic, performing the same role that mechanical relays performed historically, but with far higher speed, lower power, no contact bounce, and essentially infinite mechanical life. The 74LV4053 belongs to the broader category of multiplexer/demultiplexer (MUX/DEMUX) ICs, which themselves fall under the interface ICs hierarchy within the integrated-circuit taxonomy.
Key differentiating features include very low quiescent current (a few microamps at 25 °C), fast switching with typical turn-on (tON) of 190 ns and turn-off (tOFF) of 125 ns at 3 V, 5 ohm on-resistance matching between channels (Delta-RON), and 50 dB off-isolation (VISO) at typical audio frequencies. The device is pin- and function-compatible with the higher-voltage 74HC4053 and 74HCT4053 families, allowing direct substitution in existing footprints when a lower-voltage rail is acceptable. Integrated logic-level translation also makes it suitable for interfacing 5 V controllers with 1.8 V or 3.3 V peripherals.
Architecturally, the 74LV4053D uses N-channel and P-channel MOSFET pairs in a transmission-gate topology for each of the three switches; the CMOS process delivers bidirectional signal handling from rail to rail, low charge injection, and high input impedance for both analog and digital signals. Because all switches share a common substrate, designers should observe standard ESD handling precautions and avoid signal voltages that exceed VDD7.
Typical applications include audio signal routing in portable consumer devices, multiplexing sensor outputs to a microcontroller ADC, video or composite signal switching, communication line routing, and general-purpose signal-path selection in industrial and automotive subsystems. The wide 1.0 V to 6.0 V supply range makes the part equally comfortable in coin-cell powered IoT nodes and 5 V legacy systems.
When designing with this device, ensure that the analog signal swing remains within the VDD and GND rails to prevent latch-up of the internal transmission-gate MOSFETs. Add 100 nF ceramic bypass capacitors adjacent to VDD and GND, and route digital select lines away from sensitive analog traces to preserve the 50 dB off-isolation figure.
This page consolidates distributor pricing, verified drop-in alternatives, and practical design notes that are not assembled in the manufacturer short datasheet, providing engineers with a single source for procurement and design decisions.
ドロップイン代替品: 74LV4053D,118 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
74LV4053D,112
✅ ドロップイン📋 参考代替品（カタログ未掲載）
74HC4053D,653
✅ ドロップイン📋 参考代替品（カタログ未掲載）
74HCT4053D,653
✅ ドロップイン📋 参考代替品（カタログ未掲載）
CD4053BM96
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MC74HC4053ADR2G
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX4053AC3
✅ ドロップイン📋 参考代替品（カタログ未掲載）
74LV4053D,118 最大定格＆電気的特性
| 機能 | Triple SPDT analog switch / 2:1 multiplexer-demultiplexer |
| Number of Circuits | 3 |
| Configuration | 3 x SPDT (2:1) |
| On-Resistance (Ron) Typical | 105 ohm |
| On-Resistance (Ron) Maximum | 225 ohm |
| On-Resistance Matching (Delta-RON) | 5 ohm |
| Supply Voltage (VDD) | 1.0 V to 6.0 V |
| Switching Time tON (typ) | 190 ns |
| Switching Time tOFF (typ) | 125 ns |
| Off-Isolation (VISO) | 50 dB |
| 動作温度範囲 | -40 C to +125 C |
| パッケージ | SO-16 (SOT109) |
| 実装タイプ | Surface Mount |
| Logic Family | 74LV (Low-Voltage CMOS) |
| Compatibility | Pin- and function-compatible with 74HC4053 / 74HCT4053 |
| Application Class | Automotive qualified |
| RoHS ステータス | Compliant |
74LV4053D,118 ピン構成
| ピン 1 | 1Y0 — Channel 1, input/output 0 |
| ピン 2 | 2Y0 — Channel 2, input/output 0 |
| ピン 3 | Z2 — Channel 2, common input/output |
| ピン 4 | Z1 — Channel 1, common input/output |
| ピン 5 | 2Y1 — Channel 2, input/output 1 |
| ピン 6 | 1Y1 — Channel 1, input/output 1 |
| ピン 7 | VEE — Negative supply (typically GND for unipolar operation) |
| ピン 8 | GND — Ground (0 V) |
| ピン 9 | Z3 — Channel 3, common input/output |
| ピン 10 | S3 — Channel 3, select input |
| ピン 11 | S1 — Channel 1, select input |
| ピン 12 | S2 — Channel 2, select input |
| ピン 13 | 3Y0 — Channel 3, input/output 0 |
| ピン 14 | E — Enable input (active low) |
| ピン 15 | 3Y1 — Channel 3, input/output 1 |
| ピン 16 | VDD — Positive supply voltage (1.0 V to 6.0 V) |
主な用途
74LV4053D,118 の用途: 7 件s: Audio Signal Routing, Sensor Multiplexing to ADC, Communication Line Routing, Portable Consumer Electronics, Automotive Subsystems, Industrial Signal Selection, Test and Measurement Front-End.
Audio Signal Routing
The 74LV4053D,118 suits portable audio devices where two analog sources (e.g. line-in vs microphone) must be routed to one amplifier input. Its 105 ohm typical on-resistance adds negligible series loss for audio-band signals, while the 50 dB off-isolation at 1 kHz prevents the muted source from leaking into the active path. The 1 V to 6 V supply range aligns with single-cell Li-ion rails, and the SO-16 footprint fits alongside low-power op-amps in space-constrained headphone and Bluetooth-speaker designs.
おすすめ
Sensor Multiplexing to ADC
Three independent switches let the 74LV4053D,118 multiplex up to six single-ended sensors to one microcontroller ADC, halving ADC pin count in data-acquisition boards. Low on-resistance flatness (5 ohm matching) preserves gain calibration, and the 1.0 V minimum supply matches coin-cell powered sensor hubs. Designers typically drive the select inputs from GPIO and use the part's low quiescent current to extend battery life in IoT sensor nodes.
おすすめ
Communication Line Routing
The 74LV4053D,118 is well-suited to UART, SPI, or low-speed CAN signal steering between two buses or transceivers. Each switch is bidirectional and handles rail-to-rail signals within the VDD rail, simplifying board layout when one MCU port must serve two peripherals. Engineers confirm analog signal swings stay within 0 V to VDD to avoid transmission-gate latch-up and observe standard ESD handling on line-side pins.
おすすめ
Portable Consumer Electronics
Battery-powered consumer devices benefit from the 74LV4053D,118's 1.0 V to 6.0 V supply range, which tracks single-cell Li-ion and alkaline chemistries without level shifters. The SO-16 package draws under 1 mA quiescent current, preserving standby run-time in fitness bands, smart watches, and wireless earbuds. Designers place 100 nF ceramic bypass close to VDD and route the analog traces over a contiguous ground plane to maintain off-isolation.
おすすめ
Automotive Subsystems
The 74LV4053D,118 is qualified for automotive applications per the Nexperia 74LV4053 family datasheet, making it suitable for body controllers, instrument clusters, and infotainment signal routing. Its -40 C to +125 C operating temperature covers under-hood and cabin environments, and the SO-16 footprint is well-supported by automotive PCB layout guidelines. Engineers verify supply transients stay within the 6 V absolute maximum and add TVS protection on line-side pins for load-dump compliance.
おすすめ
Industrial Signal Selection
In PLC analog front-ends, the 74LV4053D,118 routes thermocouple, RTD, or 4-20 mA conditioned signals to one 24-bit ADC, reducing BOM cost versus per-channel ADCs. The 1 V to 6 V supply interfaces directly with 3.3 V or 5 V industrial MCUs, while the -40 C to +125 C range covers factory-floor enclosures. Designers add input-protection TVS diodes because industrial lines frequently carry ESD and surge events that exceed the part's absolute-maximum ratings.
おすすめ
Test and Measurement Front-End
Bench instruments and ATE pin-electronics benefit from the 74LV4053D,118's low Ron flatness (5 ohm matching) when steering precision reference voltages to multiple DUT paths. The 190 ns tON / 125 ns tOFF enable scan-test multiplexing without degrading measurement throughput. The 1 V to 6 V supply accommodates modern low-voltage ASICs, and the SO-16 mechanical drawing matches standard DMM and oscilloscope daughter-card footprints.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 74LV4053D,118 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 74LV4053D,112 | 74HC4053D,653 | 74HCT4053D,653 | CD4053BM96 | MC74HC4053ADR2G | MAX4053AC3 |
|---|---|---|---|---|---|---|---|
| Brand | Nexperia | Nexperia | Nexperia | Nexperia | Texas Instruments | onsemi | Analog Devices |
| Package | SO-16 (SOT109) | SO-16 - same | SO-16 - same | SO-16 - same | SOIC-16 - same | SOIC-16 - same | SOIC-16 - same |
| Supply Voltage | 1.0 V to 6.0 V | 1.0 V to 6.0 V | 2.0 V to 10.0 V | 4.5 V to 5.5 V | 3.0 V to 18.0 V | 2.0 V to 12.0 V | 2.0 V to 16.0 V |
| On-Resistance (Ron typical) | 105 ohm | 105 ohm | 200 ohm | 200 ohm | 125 ohm | 100 ohm | 60 ohm |
| Switching tON (typ) | 190 ns | 190 ns | 30 ns | 30 ns | 160 ns | 40 ns | 120 ns |
| Switching tOFF (typ) | 125 ns | 125 ns | 30 ns | 30 ns | 100 ns | 40 ns | 75 ns |
| Logic Family | 74LV (Low-Voltage CMOS) | 74LV (Low-Voltage CMOS) | 74HC (High-Speed CMOS) | 74HCT (TTL inputs) | 4000B CMOS | 74HC (High-Speed CMOS) | Low-Leakage CMOS |
| Operating Temperature | -40 C to +125 C | -40 C to +125 C | -40 C to +125 C | -40 C to +125 C | -55 C to +125 C | -55 C to +125 C | -40 C to +85 C |
| RoHS / Lead-Free | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes |
主な差別化要因
- Widest low-voltage supply range in the SO-16 SPDT family （vs 74HC4053D,653)
- Verified pin-to-pin drop-in across vendors （vs CD4053BM96)
- Best channel-to-channel matching in LV-CMOS class （vs MC74HC4053ADR2G)
- Lower on-resistance at low VDD （vs MAX4053AC3)
設計ノート
Place a 100 nF X7R ceramic decoupling capacitor within 3 mm of pin 16 (VDD) and a larger 1 uF to 10 uF bulk capacitor on the same node to handle transient switching current. Return the capacitor ground directly to pin 8 (GND) using a short, wide trace to minimize inductance. The Nexperia 74LV4053 datasheet recommends a contiguous ground plane under the SO-16 footprint to preserve the 50 dB off-isolation figure.
Ensure that analog signal swings at nY0, nY1, and nZ remain within the VDD and GND rails at all times, including during power-up and power-down transients. Exceeding these rails forward-biases the internal ESD diodes and may cause transmission-gate latch-up. For input signals outside the supply range, use the Nexperia 74LV4053 in conjunction with external clamping or level-shift to a compatible voltage.
Route the S1, S2, S3 select lines and the active-low enable pin away from sensitive analog traces to avoid capacitive crosstalk into the analog signal path. Maintain at least 3 trace widths of separation between digital select traces and analog Y/Z traces. The 190 ns tON / 125 ns tOFF edges contain high-frequency harmonics that couple through PCB stray capacitance, so guarding with ground traces is recommended for high-impedance analog nodes.
Do not operate the 74LV4053D,118 with analog signals greater than VDD or below GND. When migrating from 74HC4053 designs to the 74LV4053D,118, verify that the existing analog signal swing fits within the new 6 V absolute maximum. Also note that the ,118 suffix denotes 13-inch reel packing per Nexperia / NXP packaging conventions; engineers hand-prototyping should order the ,112 tube-packed variant instead.
コンプライアンス情報
RoHS and lead-free per Nexperia product page; the 74LV4053 family is automotive-qualified per Nexperia datasheet, but specific Q100 grade should be confirmed against the lot-level documentation. Reach compliance per EU REACH SVHC declaration.
