874003BG-05LF - 320MHz PCIe Jitter Attenuator | Renesas
部品番号: 874003BG-05LF ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.5 | $6.50 |
| 10 | $5.85 | $58.50 |
| 100 | $5.2 | $520.00 |
| 500 | $4.6 | $2,300.00 |
| 1,000 | $4.1 | $4,100.00 |
874003BG-05LF 概要
A jitter attenuator is a clock-domain device that cleans the phase noise of an incoming reference clock and regenerates a high-purity low-jitter signal. It sits between an upstream oscillator or PLL and downstream logic (SerDes, PCIe PHYs, ASICs), where cycle-to-cycle timing variation directly impacts link bit-error-rate. PCI Express specifications demand very tight PCIe Gen 2/3 jitter budgets, making FemtoClock-class jitter attenuators a common solution. The 874003 family belongs to a broader Renesas clock-IC portfolio that includes fanout buffers, synthesizers, and frequency multipliers used across networking and computing.
Key specifications include 320MHz maximum input/output frequency, differential HCSL/LVDS/LVHSTL input compatibility, low additive jitter from the FemtoClock PLL, single 3.3V supply operation, and industrial 0°C to +70°C commercial temperature grade. The 20-pin TSSOP package saves board area compared with QFN alternatives and is well suited to compact PCIe add-in cards.
Typical applications include PCI Express add-in cards, server motherboards, networking switches and routers, embedded computing platforms, and storage controllers that require a low-jitter PCIe reference clock sourced from a noisy system clock domain.
Designers should pay attention to power-supply decoupling and output trace impedance when integrating this part. Place 0.1µF ceramic bypass capacitors close to each supply pin and maintain 100-ohm differential routing on the HCSL outputs to meet PCIe compliance.
This page synthesizes current distributor pricing, drop-in alternatives from the same Renesas 874003 family and cross-brand PCIe jitter attenuators, plus practical layout and decoupling notes not consolidated in the manufacturer datasheet.
ドロップイン代替品: 874003BG-05LF — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
874003AGI-05LF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
874003BGILF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
874003BGI-05LF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
874003AG-05LF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
874001AGI-05LF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
9DBL0841
✅ ドロップイン📋 参考代替品（カタログ未掲載）
874003BG-05LF 仕様
| 機能 | PCI Express Fanout Buffer / Jitter Attenuator |
| PLL Technology | FemtoClock (3rd Generation) |
| Main Purpose | PCI Express (PCIe) |
| Maximum Frequency | 320 MHz |
| 出力数 | 1 |
| Input Signal Type | HCSL, LVDS, LVHSTL |
| Output Signal Type | HCSL (PCIe compliant) |
| 電源電圧 | 3.3 V |
| 動作温度 | 0°C to +70°C (commercial) |
| パッケージ | 20-pin TSSOP |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| Lead-Free | Yes |
874003BG-05LF ピン構成
| ピン 1 | VDD — 3.3V supply |
| ピン 2 | GND — Ground |
| ピン 3 | CLK — Differential clock input (positive) |
| ピン 4 | nCLK — Differential clock input (negative) |
| ピン 5 | VDD — 3.3V supply (PLL core) |
| ピン 6 | GND — Ground |
| ピン 7 | PLL_BYPASS — PLL bypass control |
| ピン 8 | FREQSEL — Frequency select configuration |
| ピン 9 | OE — Output enable (active high) |
| ピン 10 | GND — Ground |
| ピン 11 | Q — Differential HCSL output (positive) |
| ピン 12 | nQ — Differential HCSL output (negative) |
| ピン 13 | GND — Ground |
| ピン 14 | VDD — 3.3V supply (output driver) |
| ピン 15 | NC — Not connected (per datasheet) |
| ピン 16 | NC — Not connected (per datasheet) |
| ピン 17 | TEST — Factory test pin (tie to GND) |
| ピン 18 | FSEL0 — Frequency select bit 0 |
| ピン 19 | FSEL1 — Frequency select bit 1 |
| ピン 20 | GND — Ground |
主な用途
874003BG-05LF の用途: 6 件s: PCI Express Add-in Cards, Server Motherboards, Networking Switches and Routers, Embedded Computing Platforms, Storage Controllers (NVMe/SAS HBAs), Industrial Computing and Test Equipment.
PCI Express Add-in Cards
The 874003BG-05LF's 320MHz FemtoClock PLL and PCIe-compliant HCSL output make it the reference-clock solution for PCIe add-in cards where board area is constrained by the 20-pin TSSOP footprint. Its single-output topology matches the standard 100MHz PCIe reference clock distributed to one downstream PHY. The low additive jitter from the 3rd-gen FemtoClock architecture ensures compliance with PCIe Gen 2 jitter budgets (under 3ps RMS), which directly improves link BER. Designers place the part adjacent to the PCIe connector/edge-finger side, with 100-ohm differential routing on the HCSL pair to the PHY.
おすすめ
Server Motherboards
On server motherboards, the 874003BG-05LF provides a clean PCIe reference clock sourced from a system clock generator, isolating downstream PHYs from noisy system clock domains. The 3.3V single-supply operation simplifies power-tree integration alongside other clock-tree ICs. With sub-picosecond additive jitter, the device supports PCIe Gen 2/3 endpoints used in mainstream server CPUs. Place near the PCIe slot connectors with matched-length differential traces and a 0.1uF decoupling cap per supply pin.
おすすめ
Networking Switches and Routers
Networking switches use the 874003BG-05LF to clean the 100MHz reference clock before distributing to multiple Ethernet PHY or switch ASIC PCIe interfaces. The FemtoClock PLL rejects phase noise from the upstream switch clock tree, ensuring jitter-compliance on PCIe links to management processors and fabric ASICs. The single-output configuration is well-suited to dedicated PCIe lanes used for switch CPU communication. Industrial-grade variants are available for outdoor or ruggedized switch chassis.
おすすめ
Embedded Computing Platforms
Embedded computing platforms (COM Express, SMARC, single-board computers) use the 874003BG-05LF to generate a low-jitter PCIe reference for onboard Mini-PCIe or M.2 slots. Its 20-pin TSSOP package fits in compact SoM layouts, while the 0-70C commercial temperature grade covers most indoor edge-compute environments. The device accepts HCSL/LVDS/LVHSTL inputs, making it compatible with common SoC clock outputs.
おすすめ
Storage Controllers (NVMe/SAS HBAs)
NVMe SSD enclosures and SAS/SATA HBA cards use the 874003BG-05LF to provide a clean PCIe reference clock to the storage controller ASIC, where PCIe link jitter directly affects storage throughput. The single-output topology suits the single PCIe uplink typical of storage cards. The FemtoClock PLL attenuates phase noise from upstream PCIe clock distribution, supporting PCIe Gen 3 storage performance targets.
おすすめ
Industrial Computing and Test Equipment
Industrial PCs and test/measurement equipment use the 874003BG-05LF for its reliability and FemtoClock jitter performance in PCIe-based data-acquisition cards. The commercial 0-70C temperature grade covers most lab and factory-floor environments, while industrial -40 to +85C variants are available within the 874003 family for harsher deployments. The single-output HCSL signal drives the PCIe PHY directly with deterministic jitter.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 874003BG-05LF — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 874003AGI-05LF | 874003BGILF | 874003BGI-05LF | 874003AG-05LF | 874001AGI-05LF | 9DBL0841 |
|---|---|---|---|---|---|---|---|
| Package | 20-pin TSSOP | 20-pin TSSOP | 20-pin TSSOP | 20-pin TSSOP | 20-pin TSSOP | 20-pin TSSOP | 20-pin TSSOP |
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Max Frequency | 320 MHz | 320 MHz | 320 MHz | 320 MHz | 320 MHz | 200 MHz | 200 MHz |
| Output Count | 1 | 1 | 1 | 1 | 1 | 1 | 8 |
| Input Type | HCSL / LVDS / LVHSTL | HCSL / LVDS / LVHSTL | HCSL / LVDS / LVHSTL | HCSL / LVDS / LVHSTL | HCSL / LVDS / LVHSTL | HCSL / LVDS | HCSL |
| Operating Temperature | 0°C to +70°C (commercial) | 0°C to +70°C | -40°C to +85°C (industrial) | -40°C to +85°C (industrial) | 0°C to +70°C | -40°C to +85°C | 0°C to +70°C |
| PLL Technology | FemtoClock 3rd Gen | FemtoClock 3rd Gen | FemtoClock 3rd Gen | FemtoClock 3rd Gen | FemtoClock 3rd Gen | FemtoClock 2nd Gen | FemtoClock 3rd Gen |
| Target Use | PCIe Gen 2/3 jitter attenuator | PCIe Gen 2/3 | PCIe Gen 2/3 | PCIe Gen 2/3 | PCIe Gen 2/3 | PCIe Gen 1/2 | PCIe Gen 3 multi-output |
| Approx. Unit Price @ qty 100 (USD) | $5.20 | $5.50 | $7.20 | $6.80 | $5.50 | $4.90 | $8.40 |
主な差別化要因
- 3rd-Generation FemtoClock PLL with sub-picosecond additive jitter （vs 874001AGI-05LF)
- Multi-standard input compatibility (HCSL/LVDS/LVHSTL) （vs 9DBL0841)
- Single-output TSSOP-20 footprint vs. multi-output alternatives （vs 9DBL0841)
設計ノート
Place a 0.1µF X7R ceramic decoupling capacitor within 2mm of each VDD pin (pins 1, 5, 14), plus a single 10µF bulk capacitor at the regulator output. The FemtoClock PLL is sensitive to supply noise - noisy rails couple directly into jitter. Star-route the 3.3V supply from the regulator and avoid sharing the trace with high-current switching loads.
Maintain 100Ω differential impedance on the HCSL output pair (Q/nQ) and on the input pair (CLK/nCLK). Match trace lengths within 5 mils to minimize intra-pair skew. Keep output traces away from switching power and high-speed digital buses; route over a continuous ground reference plane. Place the part close to the downstream PCIe PHY to minimize stub effects.
AC-couple the CLK/nCLK input pair (typically 0.1µF series caps) when using LVDS or LVHSTL sources. For HCSL inputs, follow the standard 100Ω source-termination scheme specified in the PCIe CEM specification. Verify additive jitter with a phase-noise analyzer or jitter decomposition tool to confirm compliance with PCIe Gen 2/3 jitter budgets.
Do not leave the OE (output enable) pin floating - tie it high for normal operation or low for high-impedance output. Verify FSEL0/FSEL1 logic levels match the desired frequency before layout tape-out; misconfigured frequency select pins are a leading cause of PCIe compliance failures. The TEST pin (pin 17) must be tied to GND for normal operation per the datasheet.
The 20-pin TSSOP package has modest power dissipation (~150mW typical). At maximum output loading and elevated ambient, junction temperature rise is approximately 25-30°C above ambient. For industrial deployments in enclosed chassis, verify the theta-JA derating against the operating environment. The TSSOP thermal pad is not exposed; use component-side copper pour for additional heat spreading.
コンプライアンス情報
RoHS compliant and lead-free per Renesas product page. Not AEC-Q100 qualified (commercial grade only). Industrial temperature variants available in same family.
