A42MX24-3PLG84I - 36K Gate FPGA 84-PLCC | Microchip
部品番号: A42MX24-3PLG84I ⚠ ラストタイムバイ| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $62 | $62.00 |
| 10 | $57.5 | $575.00 |
| 100 | $52 | $5,200.00 |
| 500 | $47 | $23,500.00 |
| 1,000 | $43.5 | $43,500.00 |
A42MX24-3PLG84I 概要
A field programmable gate array (FPGA) is an integrated circuit that engineers configure after manufacturing to implement custom digital logic. The MX family sits within the broader taxonomy of FPGA > programmable logic device > semiconductor, and unlike SRAM-based FPGAs, its antifuse-based programming is non-volatile and radiation-tolerant by construction, requiring no configuration device at power-up.
Key features include 36K system gates with D-modules arranged around the device periphery providing fast, wide-input AND decode functions similar to CPLD architectures, an efficient flexible 5.0V-tolerant architecture, and legacy PLD integration on a single low-cost device. Speed grade -3 denotes the fastest commercial/industrial bin in the family. The 84-PLCC (29.31x29.31 mm) surface-mount package offers through-hole-like mechanical robustness favored in aerospace, industrial, and defense retrofits.
Architecturally, the device combines combinatorial R-modules, sequential C-modules, and wide-decode D-modules, enabling glue logic consolidation, bus interfacing, and state-machine implementation with deterministic timing. Microsemi (now Microchip) positioned MX as a high-volume ASIC replacement platform.
Typical applications include legacy system obsolescence redesign, industrial control glue logic, military/aerospace interface bridging, and communications backplane control.
Design consideration: verify power sequencing of the 3.3V and 5.0V rails and confirm last-time-buy status against your lifecycle plan, as the MX family is in end-of-life transition. Prices as of 2026-08-30.
ドロップイン代替品: A42MX24-3PLG84I — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: A42MX24-3PLG84I （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Family, System Gates, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
A42MX24-3PLG84
✅ ドロップイン✓ 在庫あり
$44.2 / 個
データシートを見る →A42MX24-2PLG84I
✅ ドロップイン✓ 在庫あり
$55.4 / 個
データシートを見る →A42MX16-3PLG84
✅ ドロップイン✓ 在庫あり
$1 / 個
データシートを見る →A42MX16-2PLG84I
✅ ドロップイン✓ 在庫あり
$30.8 / 個
データシートを見る →A42MX09-3PLG84
✅ ドロップイン✓ 在庫あり
$22.8 / 個
データシートを見る →A42MX16-1PLG84I
✅ ドロップイン✓ 在庫あり
$1 / 個
データシートを見る →A42MX24-3PLG84I 最大定格＆電気的特性
| Family | 42MX |
| System Gates | 36000 |
| Logic Cells | 912 |
| Process Technology | 0.45 um |
| 電源電圧 | 3V ~ 3.6V, 4.75V ~ 5.25V |
| Speed Grade | -3 |
| User I/O | 72 |
| パッケージ | 84-LCC (J-Lead) / 84-PLCC (29.31x29.31 mm) |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +85C (industrial, -I suffix) |
| Programming Technology | Antifuse (non-volatile) |
| RoHS ステータス | ROHS3 Compliant |
| Lead Free | Yes |
| Packaging | Tray |
A42MX24-3PLG84I 84-lcc (j-lead) / 84-plcc (29.31x29.31 mm) ピン配置ガイド
A42MX24-3PLG84I (84-lcc (j-lead) / 84-plcc (29.31x29.31 mm) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: A42MX24-3PLG84I.
詳細は データシート をご参照ください。
主な用途
A42MX24-3PLG84I の用途: 6 件s: Legacy System Obsolescence Redesign, Aerospace and Defense Interface Logic, Industrial Control Glue Logic, Communications Backplane Control, Test and Measurement Fixture Logic, ASIC Prototyping and Low-Volume Bridge.
Legacy System Obsolescence Redesign
The MX family is Microsemi's designated platform for integrating legacy PLDs and discontinued logic into a single chip. With 36K gates, dual 3.3V/5V operation, and the mechanically robust 84-PLCC package, the A42MX24-3PLG84I can absorb multiple 22V10-class PLDs, bus transceivers' glue logic, and address decoders while remaining pin-compatible with older MX-based boards. Its antifuse programming is non-volatile, so retrofitted systems power up instantly without configuration devices - a key requirement when replacing components in equipment that must boot unattended.
おすすめ
Aerospace and Defense Interface Logic
Actel/Microsemi antifuse FPGAs have a long heritage in defense and aerospace programs because their antifuse interconnect resists configuration upsets and needs no external boot flash. The industrial-temperature A42MX24-3PLG84I provides 36K gates of deterministic-logic for bus interface bridging, discrete I/O conditioning, and wide-decode functions via D-modules that emulate CPLD-style fast AND arrays. The 5V-tolerant architecture directly interfaces MIL-style 5V signaling, and the PLCC J-lead package withstands vibration better than fine-pitch QFP alternatives.
おすすめ
Industrial Control Glue Logic
In industrial controllers, PLC I/O cards, and motor-drive backplanes, the A42MX24-3PLG84I consolidates address decoding, interrupt arbitration, and status multiplexing that previously occupied several SSI/MSI devices. The dual 3.3V/5V supply ranges (3V~3.6V and 4.75V~5.25V) let it sit directly on legacy 5V control buses without level translators, while 912 logic cells and D-module wide-decode deliver fast, deterministic decode times. Its instant-on antifuse configuration eliminates boot-delay concerns in machines that must respond at power-up.
おすすめ
Communications Backplane Control
Telecom and datacom line cards historically used MX FPGAs for backplane handshaking, board identification, and hot-swap control sequencing. The A42MX24-3PLG84I's 72 user I/O and 36K gates implement JTAG boundary-scan-friendly control fabrics with wide-input AND decode for address and slot identification. Because the antifuse fabric is write-once and non-volatile, line cards recover instantly after power cycles or shelf storage - unlike SRAM FPGAs that need reconfiguration - reducing field MTTR in carrier-grade equipment.
おすすめ
Test and Measurement Fixture Logic
Bed-of-nails fixtures and automated test equipment benefit from the A42MX24-3PLG84I as a reprogrammable (one-time) but re-manufacturable decode resource: fixtures can be rebuilt with fresh devices per test revision. Wide-decode D-modules give fast channel-select AND functions with predictable propagation, important for timing-accurate stimulus routing. The 5V-tolerant I/O interfaces directly with legacy TTL-level test signals, and the PLCC socket-compatible package lets fixtures swap devices without soldering during calibration.
おすすめ
ASIC Prototyping and Low-Volume Bridge
Microchip markets MX as a reliable, single-chip ASIC alternative for high-volume, low-cost integration. Before ASIC tape-out, the A42MX24-3PLG84I prototypes control-plane logic of approximately 36K gates; the same netlist maps to production MX devices for bridge production. The 0.45 um antifuse process offers gate-level timing close to the original ASIC library targets, and the -3 speed grade minimizes timing closure risk. For volumes too low for ASIC economics, MX becomes the permanent production silicon itself.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: A42MX24-3PLG84I — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | A42MX24-3PLG84 | A42MX24-2PLG84I | A42MX16-3PLG84 | A42MX09-3PLG84 |
|---|---|---|---|---|---|
| Package | 84-PLCC (J-Lead) | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same |
| Brand | Microchip Technology (Microsemi) | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| System Gates | 36000 | 36000 | 36000 | 24000 | 9000 |
| Logic Cells | 912 | 912 | 912 | 608 | 228 |
| Speed Grade | -3 (fastest) | -3 | -2 | -3 | -3 |
| Supply Voltage | 3.3V / 5V dual | 3.3V / 5V dual | 3.3V / 5V dual | 3.3V / 5V dual | 3.3V / 5V dual |
| Lifecycle Status | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy |
主な差別化要因
- Fastest -3 speed grade with industrial rating （vs A42MX24-2PLG84I)
- Maximum density available in the 84-PLCC footprint （vs A42MX16-3PLG84)
- Industrial temperature for harsh environments （vs A42MX24-3PLG84)
設計ノート
The A42MX24-3PLG84I requires dual supplies: 3.3V (3V~3.6V) for core/output and 5V (4.75V~5.25V) per the 40MX/42MX datasheet DS2316. Verify rail sequencing against your board's power tree; add 0.1uF ceramic decoupling per supply pin plus bulk 10uF at the device. The 5V tolerance is a key legacy advantage, but do not mix 5V inputs on a 3.3V-only bank - consult the datasheet I/O configuration tables.
This part is antifuse-programmed and one-time programmable: an incorrect bitstream permanently consumes the device. Always validate the design fully in simulation (Libero/Microchip design tools) and, if possible, on a commercial-temperature A42MX24-3PLG84 before programming industrial units. Also confirm timing closure at speed grade -3; if slack is thin, the -2 or -1 grade parts will not meet timing as drop-ins.
The 84-PLCC J-lead package is socket-compatible, which simplifies field replacement but adds contact inductance; keep JTAG TCK lines short and series-terminate if the chain exceeds a few inches. Provide a solid ground plane under the PLCC and follow the DS2316 PLG84 mechanical drawing (29.31x29.31 mm) for land pattern dimensions to ensure socket compatibility.
コンプライアンス情報
ROHS3 Compliant per Microchip USA product listing; LEAD FREE per PCB Electronics listing.
