A42MX24-PL84 - 36K Gate FPGA, 84-PLCC | Microchip Technology
部品番号: A42MX24-PL84 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $194.4 | $194.40 |
| 10 | $184.68 | $1,846.80 |
| 100 | $174.96 | $17,496.00 |
| 500 | $165.24 | $82,620.00 |
| 1,000 | $155.52 | $155,520.00 |
A42MX24-PL84 概要
An FPGA (Field-Programmable Gate Array) is a semiconductor device containing a fabric of configurable logic blocks and programmable interconnects that the designer configures after manufacturing. Within the programmable-logic hierarchy (FPGA -> programmable logic device -> digital IC), FPGAs sit between fixed-function ASICs and CPLDs. The MX family is specifically positioned as a reliable, single-chip ASIC alternative and an ideal platform for integrating legacy PLDs into a single low-cost device, thanks to its flexible 5.0V-tolerant architecture.
Key features include the 42MX modular architecture with C-modules (combinatorial), R-modules (sequential/registers), and on the A42MX24, D-modules arranged around the device periphery that provide fast wide-input decode functions similar to CPLD-style wide-decode circuitry. The device is antifuse-programmable, giving non-volatile configuration, high design security, and instant-on behavior without external configuration memory - a differentiator over SRAM FPGAs. Dual 3.3V/5V supply operation simplifies interfacing with legacy 5V systems.
The architecture delivers deterministic, low-skew routing with high performance for glue logic, bus interfacing, address decoding, state machines, and system integration tasks. Typical applications include industrial control, legacy PLD consolidation, 5V-system interfacing, aerospace/defense upgrades of obsolete designs, and high-volume cost-sensitive systems replacing ASIC NRE.
Design consideration: the PLCC-84 package offers moderate I/O density; verify supply sequencing of the 3.3V and 5V rails and follow the 40MX/42MX FPGA Families datasheet (DS2316) power and layout recommendations. Pricing referenced as of 2026-08-30.
ドロップイン代替品: A42MX24-PL84 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
A42MX24-PL84I
✅ ドロップイン📋 参考代替品（カタログ未掲載）
A42MX24-1PL84M
✅ ドロップイン📋 参考代替品（カタログ未掲載）
A42MX24-2PLG84IX39
✅ ドロップイン📋 参考代替品（カタログ未掲載）
A42MX36-PL84
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
A42MX09-PL84
⚡ 同一パッケージ ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
A42MX24-PL84 最大定格＆電気的特性
| Family | 42MX (MX FPGA) |
| System Gates | 36000 |
| Logic Cells | 912 |
| User I/O | 72 |
| Process Technology | 0.45 um CMOS |
| Supply Voltage 1 | 3.0 V to 3.6 V |
| Supply Voltage 2 | 4.75 V to 5.25 V |
| パッケージ | 84-LCC (J-Lead) / 84-PLCC |
| 実装タイプ | Surface Mount |
| Programming Technology | Antifuse (non-volatile) |
| Module Types | C-modules, R-modules, D-modules (wide decode) |
| Configuration Memory | Internal, non-volatile (no external config device required) |
| RoHS ステータス | unknown |
| Typical Applications | ASIC replacement, legacy PLD integration, 5V system interfacing |
A42MX24-PL84 84-lcc (j-lead) / 84-plcc ピン配置ガイド
A42MX24-PL84 (84-lcc (j-lead) / 84-plcc パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: A42MX24-PL84.
詳細は データシート をご参照ください。
主な用途
A42MX24-PL84 の用途: 6 件s: Legacy PLD Consolidation, Industrial Control Systems, ASIC Prototyping and Low-Volume Replacement, Aerospace and Defense Obsolescence Upgrades, Bus Interfacing and Glue Logic, Test and Measurement Equipment.
Legacy PLD Consolidation
The A42MX24-PL84 directly addresses Microchip's stated MX family mission: integrating legacy PLDs into a single low-cost device. Its 36,000 gates and 912 cells absorb multiple 22V10-class PAL/GAL devices and small CPLDs, while D-module wide-decode circuitry accelerates address decoding and chip-select functions. Dual 3.3V/5V supplies let the fabric interface directly with 5V legacy buses without level shifters, and antifuse non-volatile configuration eliminates external configuration memory, simplifying board-level replacement of older multi-chip logic clusters.
おすすめ
Industrial Control Systems
Industrial controllers built around 5V logic benefit from the A42MX24-PL84's 4.75V-5.25V supply tolerance and 72 configurable I/O. The antifuse fabric gives instant-on operation - no configuration boot delay - which matters for machine safety interlocks and motor sequencing logic that must be valid at power-up. Its 0.45um process with mature reliability data suits long-lifecycle factory equipment, and deterministic routing supports fixed-timing state machines. According to the DS2316 datasheet, D-modules provide fast wide-input decode ideal for PLC I/O map decoding.
おすすめ
ASIC Prototyping and Low-Volume Replacement
Microchip positions MX FPGAs as a reliable, single-chip ASIC alternative. For gate arrays between roughly 10K and 50K gates where ASIC NRE is unjustified, the A42MX24-PL84 provides one-time-programmable implementation with ASIC-like security - the configured bitstream cannot be extracted, unlike SRAM FPGAs. At 36,000 gates and 912 cells it suits medium-glue-logic ASIC replacements. The PLCC-84 package supports socketed prototyping, and pricing near $194 as of 2026-08-30 makes low-volume runs economically viable versus mask-charge ASICs.
おすすめ
Aerospace and Defense Obsolescence Upgrades
The 42MX family includes military temperature variants (A42MX24-1PL84M, -55C to +125C per Microchip USA), making the family a standard choice for defense platforms extending the life of legacy 5V systems. Antifuse devices are inherently radiation-tolerant in configuration (no configuration memory upset) and require no external boot device, improving system-level reliability. When an obsolete Actel 1200XL or 3200DX must be replaced, Microchip's migration application note recommends 42MX equivalents, frequently available in matching packages, preserving PCB footprints in military hardware.
おすすめ
Bus Interfacing and Glue Logic
With 72 user I/O and CPLD-style wide-decode D-modules, the A42MX24-PL84 excels at bus bridging, address decoding, wait-state generation, and interrupt control between microprocessors and peripherals. The 3.3V/5V dual-supply architecture allows a single device to straddle a 5V microprocessor bus and 3.3V peripheral bank without external translators - eliminating several SN74LVC translation devices per design. Deterministic pin-to-pin delays in the antifuse fabric let designers meet hard setup/hold budgets that timing-closure-challenged SRAM FPGAs may not guarantee on small designs.
おすすめ
Test and Measurement Equipment
Bench instruments and automated test fixtures need reconfigurable sequencing, trigger logic, and interface handshaking that the A42MX24-PL84 supplies economically. Instant-on antifuse configuration ensures test stimulus logic is live immediately at power-up, and the 5V rail compatibility matches older instrumentation backplanes. At 36,000 gates the fabric comfortably hosts timing generators, comparator-latch interfaces, and protocol formatters. The PLCC-84 J-lead package simplifies socketed in-circuit replacement during instrument service, an advantage over fine-pitch BGA alternatives.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: A42MX24-PL84 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | A42MX24-PL84I | A42MX24-1PL84M | A42MX24-2PLG84IX39 | A42MX36-PL84 |
|---|---|---|---|---|---|
| Package | 84-PLCC | 84-PLCC - same | 84-PLCC - same | 84-PLCC (PLG) - same footprint | 84-PLCC - same |
| Brand | Microchip Technology (Microsemi/Actel) | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| System Gates | 36000 | 36000 | 36000 | 36000 | 54000 |
| Logic Cells | 912 | 912 | 912 | 912 | 1440 |
| User I/O | 72 | 72 | 72 | 72 | 72 |
主な差別化要因
- Dual 3.3V/5V supply architecture （vs Xilinx Spartan SRAM FPGAs)
- Non-volatile antifuse configuration （vs SRAM-based FPGAs)
- D-module wide-decode fabric （vs A42MX09-PL84)
- Trade-off: mature 0.45um process （vs Modern 28nm FPGAs)
設計ノート
The A42MX24-PL84 requires two supply rails: 3.0-3.6V and 4.75-5.25V (per Microchip USA product data). Decouple each rail with at least 0.1uF ceramic plus 10uF bulk per device, placed close to the PLCC power pins. Per the 40MX/42MX datasheet DS2316, follow the specified power-up requirements for the dual rails to avoid latch-up in the 0.45um process; check the datasheet power sequencing section before finalizing the supply design.
The MX family is antifuse one-time-programmable: a programmed device cannot be reprogrammed. Fully verify the netlist via simulation and timing analysis in Libero/Designer before committing production devices. Reserve any required future revisions by ordering unprogrammed parts. Also confirm the exact speed grade suffix when purchasing - speed grades are ordered-code specific and not field-upgradable.
PLCC-84 J-lead pads require the correct footprint per the DS2316 mechanical drawing (about 0.65mm lead width, 1.27mm pitch). For socketed prototypes use only PLCC sockets specified for 84-position J-lead devices, as poor socket contacts cause intermittent I/O failures. Keep high-fanout decode nets (D-module outputs) short to exploit the wide-decode speed advantage.
When migrating from Actel 1200XL/3200DX devices, consult Microchip's 'Migrating From 1200XL and 3200DX to 42MX FPGAs' application note: most equivalent packages exist, but some legacy packages have no 42MX equivalent, forcing a package change. Verify I/O assignments map to compatible MX bank locations during porting.
コンプライアンス情報
Compliance status not stated in verified web data; confirm on the official Microchip product page compliance summary for the exact ordering code.
