AD7177-2 - 32-bit 10 kSPS Sigma-Delta ADC | Analog Devices
部品番号: AD7177-2 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $21.5 | $21.50 |
| 10 | $19.85 | $198.50 |
| 100 | $17.9 | $1,790.00 |
| 500 | $15.45 | $7,725.00 |
| 1,000 | $13.2 | $13,200.00 |
AD7177-2 概要
A sigma-delta ADC is a high-resolution oversampling converter that uses a modulator and digital filter to exchange conversion speed for noise performance. The AD7177-2 belongs to the precision ADC family, which sits within the data converter hierarchy (ADC -> data converter -> mixed-signal IC -> semiconductor). It is engineered for low-frequency, high-precision DC measurements rather than high-speed waveform digitization.
Key features include integrated true rail-to-rail input buffers that eliminate external signal conditioning, a flexible channel sequencer, per-channel offset and gain correction registers, and a buffered reference input capable of handling up to AVDD - 1.5 V reference voltages. The digital interface is a simple SPI-/QSPI-/MICROWIRE-/DSP-compatible serial port, simplifying FPGA or microcontroller integration.
The architecture combines a third-order sigma-delta modulator with a programmable digital filter (sinc5+sinc1 or sinc3) for the optimal trade-off between noise, settling, and 50 Hz/60 Hz rejection. The integrated buffers preserve true rail-to-rail input range and allow the device to handle large common-mode or unipolar input swings directly from sensors or front-end signal chains.
Typical applications include precision weighing scales, strain-gauge bridges, industrial process control (4-20 mA loop or thermocouple digitization), medical instrumentation such as ECG and patient monitoring, chromatography and gas analysis front ends, and high-accuracy temperature measurement with PT100/RTD sensors. The 24-pin TSSOP package and integrated reference input buffer reduce external BOM, enabling compact multi-channel precision front ends.
Designers should select the AVDD supply decoupling network (typically 10 µF + 0.1 µF) and ensure the reference input bypass capacitor is placed within 5 mm of the REF+ pin to achieve datasheet noise performance. Avoid routing digital lines directly beneath analog traces to prevent digital switching noise coupling into the modulator.
This page combines official Analog Devices datasheet specifications with drop-in alternative guidance, distributor pricing tiers, and design notes not collated in a single manufacturer PDF, providing a synthesized reference for engineer evaluation and BOM selection.
ドロップイン代替品: AD7177-2 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: AD7177-2 （同一形状・フットプリント） — 相違点: Operating Temperature Range, Package, Resolution, Digital Filter, Settling Time.
クイック比較ツール — 並列比較する代替部品を選択:
AD7175-2BRUZ
✅ ドロップイン✓ 在庫あり
$9.62 / 個
データシートを見る →AD7177-2BRUZ-RL7
✅ ドロップイン✓ 在庫あり
$17.8 / 個
データシートを見る →AD7172-2BRUZ
✅ ドロップイン✓ 在庫あり
$8.64 / 個
データシートを見る →AD7173-8BRUZ
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
AD7177-2 最大定格＆電気的特性
| 分解能 | 32-bit |
| Channel Count | 2/4 (fully or pseudo differential) |
| Sample Rate | 10 kSPS/channel |
| Settling Time | 100 µs (single-cycle settling) |
| Noise-Free Bits | 19.1 bits at 10 kSPS |
| ADC Architecture | Sigma-Delta, 3rd-order modulator |
| Analog Input Buffers | True rail-to-rail, integrated |
| Analog Supply (AVDD) | 2.5 V to 5.5 V |
| Digital Supply (IOVDD) | 1.8 V to AVDD |
| Reference Input | Buffered, AVDD - 1.5 V max |
| Digital Interface | SPI / QSPI / MICROWIRE / DSP-compatible |
| Digital Filter | Sinc5+Sinc1, Sinc3 (programmable) |
| パッケージ | 24-pin TSSOP (RU-24) |
| 動作温度範囲 | -40 °C to +105 °C |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| MSL (Moisture Sensitivity Level) | 1 (unlimited) |
AD7177-2 ピン構成
| ピン 1 | DGND — Digital ground |
| ピン 2 | AVDD — Analog supply (2.5 V to 5.5 V) |
| ピン 3 | AVSS — Analog ground reference |
| ピン 4 | REF- — Reference negative input |
| ピン 5 | REF+ — Reference positive input (buffered) |
| ピン 6 | AIN0 — Analog input 0 |
| ピン 7 | AIN1 — Analog input 1 |
| ピン 8 | IOVDD — Digital I/O supply (1.8 V to AVDD) |
| ピン 9 | DGND — Digital ground |
| ピン 10 | CS — Chip select (active low) |
| ピン 11 | SCLK — Serial clock input |
| ピン 12 | DOUT/RDY — Serial data output / ready (active low) |
| ピン 13 | DIN — Serial data input |
| ピン 14 | DRDY — Data ready output (active low) |
| ピン 15 | XTAL1 — Crystal oscillator input |
| ピン 16 | XTAL2 — Crystal oscillator output |
| ピン 17 | CLKIO — Clock input/output |
| ピン 18 | GPO0 — General-purpose output 0 |
| ピン 19 | GPO1 — General-purpose output 1 |
| ピン 20 | AIN2 — Analog input 2 |
| ピン 21 | AIN3 — Analog input 3 |
| ピン 22 | REFOUT — Internal reference output (optional) |
| ピン 23 | AVSS — Analog ground reference |
| ピン 24 | EP — Exposed pad - solder to analog ground |
主な用途
AD7177-2 の用途: 7 件s: Precision Weighing Scales, Industrial Process Control (4-20 mA / Thermocouple Digitization), Medical Instrumentation (ECG, Patient Monitoring), Chromatography and Gas Analysis, RTD / PT100 Temperature Measurement, Strain-Gauge Bridge Signal Chains, Precision Data Acquisition Modules.
Precision Weighing Scales
The AD7177-2's 19.1 noise-free bits at 10 kSPS and 100 µs single-cycle settling make it well-suited to high-precision load-cell signal chains. With its integrated true rail-to-rail input buffers, the device accepts the small differential output of a strain-gauge bridge directly, eliminating an external instrumentation amplifier and reducing BOM. Channel sequencer logic enables automatic zero, span, and weighing calibration cycles across 2 load cells. Compared to a discrete PGA-plus-ADC approach, the AD7177-2 reduces board area by ~40% while achieving noise performance suitable for 100 000-count resolution scales.
おすすめ
Industrial Process Control (4-20 mA / Thermocouple Digitization)
The AD7177-2 fits 16-bit-plus process control front ends requiring channel multiplexing and high noise rejection. With its sinc5+sinc1 digital filter, the ADC achieves simultaneous 50 Hz and 60 Hz mains rejection at lower output data rates, critical for thermocouple digitizers operating near power-line interference. Per-channel offset and gain correction registers simplify scaling multiple sensor types (RTD, TC, voltage, current) sharing the same ADC. The 32-bit resolution preserves dynamic range across the 0-100 % process variable span without software scaling tricks.
おすすめ
Medical Instrumentation (ECG, Patient Monitoring)
In patient monitoring front ends, the AD7177-2's 32-bit resolution captures sub-mic rovolt biopotential signals with high dynamic range. The integrated rail-to-rail buffers accept DC-coupled electrode signals directly, simplifying the analog front end for ECG, EEG, and SpO2 modules. Its 19.1 noise-free bits at full speed and 50 Hz/60 Hz rejection from the digital filter support diagnostic-grade signal acquisition. Multiple pseudo differential inputs allow simultaneous lead-I/II/III monitoring from a single ADC, reducing component count in portable medical devices.
おすすめ
Chromatography and Gas Analysis
Gas chromatographs and mass-spectrometer front ends demand precision ADC channels with low noise and good linearity for detector signal quantification. The AD7177-2's 32-bit resolution and per-channel gain/offset calibration enable direct interface to flame ionization, thermal conductivity, and photo-ionization detectors without external range switching. Channel sequencing simplifies multi-stream gas sampling systems where 2-4 channels are scanned at fixed intervals. Excellent DC linearity and low integral non-linearity (INL) ensure quantification accuracy across the dynamic range required by ppm-level concentration measurements.
おすすめ
RTD / PT100 Temperature Measurement
High-accuracy 4-wire RTD and PT100/PT1000 temperature measurement benefits from the AD7177-2's low-noise performance and integrated input buffers. The 32-bit dynamic range resolves sub-millikelvin temperature changes when paired with a precision current source. Pseudo differential input modes simplify the 4-wire RTD Kelvin connection by using two ADC channels for differential and common-mode rejection. Combined with the ADC's per-channel calibration, factory-trimmed accuracy better than ±0.1 °C is achievable from -200 °C to +850 °C PT100 spans.
おすすめ
Strain-Gauge Bridge Signal Chains
The AD7177-2 is well-matched to load-cell and pressure-sensor bridge signal chains that require true rail-to-rail input handling. Its integrated buffers allow direct connection to bridge outputs with up to ±AVDD common-mode range, eliminating external high-voltage amplifiers. The 19.1 noise-free bits at 10 kSPS provide ample resolution for pressure transducer full-scale spans from 10 kPa to 100 MPa. Per-channel offset/gain correction registers simplify system calibration and ratiometric measurement when paired with the bridge excitation supply as the reference.
おすすめ
Precision Data Acquisition Modules
Multi-channel precision DAQ modules for laboratory and bench instruments benefit from the AD7177-2's channel sequencing and SPI interface. The internal sequencer and gain/offset registers eliminate software overhead, freeing the host microcontroller or DSP to perform digital signal processing rather than ADC bookkeeping. The 10 kSPS per-channel throughput with 100 µs settling allows sampling 2-4 channels of dynamic sensor data simultaneously. Combined with the buffered reference input, the ADC supports ratiometric measurements with up to 5 V sensor excitation rails.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: AD7177-2 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | AD7175-2BRUZ | AD7177-2BRUZ-RL7 | AD7172-2BRUZ | AD7173-8BRUZ |
|---|---|---|---|---|---|
| Package | TSSOP-24 (RU-24) | TSSOP-24 (RU-24) - same | TSSOP-24 (RU-24) - same | TSSOP-24 (RU-24) - same | TSSOP-24 (RU-24) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 32-bit | 32-bit | 32-bit | 32-bit | 32-bit |
| Sample Rate (max) | 10 kSPS/channel | 10 kSPS/channel | 10 kSPS/channel | 1.25 kSPS/channel | 31.25 kSPS/channel |
| Channel Count | 2 / 4 (diff/pseudo) | 2 / 4 (diff/pseudo) | 2 / 4 (diff/pseudo) | 2 / 4 (diff/pseudo) | 8 / 16 (diff/pseudo) |
| Integrated Input Buffers | Yes (true rail-to-rail) | Yes (true rail-to-rail) | Yes (true rail-to-rail) | Yes (true rail-to-rail) | Yes (true rail-to-rail) |
| AVDD Supply Range | 2.5 V to 5.5 V | 2.5 V to 5.5 V | 2.5 V to 5.5 V | 2.5 V to 5.5 V | 2.5 V to 5.5 V |
| Noise-Free Bits @ max speed | 19.1 bits @ 10 kSPS | 20.5 bits @ 10 kSPS (lower noise) | 19.1 bits @ 10 kSPS (same die) | 22.5 bits @ 1.25 kSPS (lower speed) | 17.5 bits @ 31.25 kSPS (higher speed) |
| Operating Temperature Range | -40 °C to +105 °C | -40 °C to +105 °C | -40 °C to +105 °C | -40 °C to +105 °C | -40 °C to +105 °C |
主な差別化要因
- Higher speed than AD7172-2 while sharing the same TSSOP-24 footprint （vs AD7172-2BRUZ)
- Higher channel count with same TSSOP-24 footprint （vs AD7173-8BRUZ)
- Integrated true rail-to-rail buffers eliminate external PGAs （vs Discrete external PGA + sigma-delta ADC)
設計ノート
Decouple AVDD and IOVDD separately with 10 µF tantalum and 0.1 µF ceramic capacitors placed within 5 mm of each supply pin. The AD7177-2 datasheet specifies that an internal LDO is not present; both AVDD and IOVDD must be supplied externally. Use star-ground topology connecting AGND and DGND at a single point near the ADC to avoid digital switching noise coupling through ground bounce.
Route analog input traces differentially with matched lengths, keep them away from digital SPI lines (CS, SCLK, DIN, DOUT), and place a ground guard ring around sensitive analog pins. The TSSOP-24 exposed pad (EP) must be soldered to a continuous analog ground copper pour for thermal dissipation and to provide low-inductance return paths for the input buffer bias currents. Place the reference input bypass capacitor (typically 10 µF) as close as possible to the REF+ pin to achieve datasheet noise performance.
Do not operate the AD7177-2 with reference voltage exceeding AVDD - 1.5 V - the internal reference buffer will saturate and conversions become invalid. Ensure the SPI clock idle state matches CPHA/CPOL configuration in the ADC's interface mode register (default CPOL=1, CPHA=1). When using pseudo differential inputs, always tie the negative input to a stable common-mode voltage; floating pseudo-diff inputs cause excessive gain drift. Per Analog Devices datasheet, allow a 1 ms power-on settling before initiating conversions for guaranteed noise performance.
The sinc5+sinc1 digital filter achieves simultaneous 50 Hz and 60 Hz rejection (>80 dB) only when the master clock is synchronized to the mains frequency; verify with EVAL-AD7177-2SDZ before deployment. For channels measuring thermocouples or other low-frequency DC signals, run the sinc3 filter at 50 Hz or 60 Hz output data rate to maximize mains noise rejection. The internal sequencer's channel-switching settling time depends on the filter type and the programmed post-conversion latency - 100 µs settling is achievable in single-cycle mode for high-speed sampling.
コンプライアンス情報
RoHS and REACH compliant per Analog Devices product page. No AEC-Q100 automotive-qualified version is currently listed in the public catalog. Industrial temperature range -40 °C to +105 °C.
