AD7652ASTZRL - 16-Bit 500kSPS SAR ADC | Analog Devices
部品番号: AD7652ASTZRL ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.65 | $256.50 |
| 100 | $22.8 | $2,280.00 |
| 500 | $20.52 | $10,260.00 |
| 1,000 | $18.42 | $18,420.00 |
AD7652ASTZRL 概要
What is a SAR ADC? A successive-approximation-register analog-to-digital converter is a sampling ADC architecture that uses a binary-search algorithm against an internal DAC to resolve each analog sample into N bits. SAR ADCs trade the multi-megasample speeds of pipeline ADCs for excellent DC accuracy, low latency, and very low power consumption - making them the architecture of choice for industrial process control, instrumentation, and multi-channel data-acquisition systems where linearity and noise immunity are more important than absolute conversion rate.
Key features of the AD7652 include 500 kSPS throughput, ±2 LSB INL (typical) at 16 bits, a true bipolar-capable analog input structure, a hardware-/software-controlled power-down mode, and a flexible digital interface supporting both parallel and serial (SPI/QSPI/MICROWIRE/DSP-compatible) readback. The on-chip 2.5 V reference is trimmed to ±0.2% (typical) and is also accessible externally, allowing the part to reference other circuit blocks while simultaneously serving the ADC core. The analog supply (AVCC) accepts 4.75 V to 5.25 V, and the digital supply (DVCC) accepts 2.7 V to 5.25 V, simplifying interfacing to 3.3 V and 5 V logic families.
The internal architecture pairs a charge-redistribution DAC with a dedicated comparator and SAR logic clocked from an on-chip oscillator. Analog input is sampled through a true bipolar front end that accepts 0 V to 5 V (unipolar mode) or ±10 V / ±5 V / 0 to 10 V ranges when configured with the appropriate front-end scaling resistors. This eliminates, in many applications, the external signal-conditioning amplifier that would otherwise sit between sensor and ADC.
Typical applications include industrial process control (PLC analog input modules), multi-axis motor control position feedback, medical instrumentation front ends, weigh-scale and strain-gauge digitizers, and general-purpose multi-channel data-acquisition boards. In motor-control loops the 500 kSPS rate and deterministic latency allow phase currents to be sampled coherently with the PWM carrier. In power-quality monitoring, the simultaneous-sample-with-track-and-hold combination on the AD7652 enables accurate capture of transient waveforms without external sample-and-hold circuitry.
When designing with the AD7652, ensure the analog input is driven from a low-impedance source - typical 20 ohms or less - so that the 575 pF input capacitance settles within the acquisition window. Use a 4.7 nF ceramic decoupling capacitor on each AVCC pin placed within 5 mm of the package, and keep the analog and digital grounds joined at a single star point beneath the exposed pad of the LQFP.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with an at-a-glance view of how the AD7652ASTZRL compares to its closest pin-compatible peers.
ドロップイン代替品: AD7652ASTZRL — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
AD7652ASTRL
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AD7652ASTZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AD7652ACPZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AD7656YSTZ-1
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AD7656BSTZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AD7652ASTZRL 最大定格＆電気的特性
| 分解能 | 16 bits |
| Architecture | SAR (Successive Approximation) |
| サンプリングレート | 500 kSPS |
| Number of Channels | 1 |
| Data Interface | Parallel, Serial (SPI/QSPI/MICROWIRE/DSP-compatible) |
| Input Type | Unipolar, true bipolar-capable (configured via input scaling resistors) |
| Analog Input Range | 0 V to 5 V (unipolar); ±10 V / ±5 V with external scaling |
| Analog Supply (AVCC) | 4.75 V to 5.25 V |
| Digital Supply (DVCC) | 2.7 V to 5.25 V |
| Internal Reference Voltage | 2.5 V |
| Power-Down Mode | Hardware/software-controlled |
| 動作温度範囲 | -40 C to +85 C |
| パッケージ | 48-pin LQFP (ST package) |
| 実装タイプ | Surface Mount |
| Packaging | Tape and Reel (13-inch reel) |
| MSLレベル | 3 (168 hours) |
| RoHS ステータス | Compliant |
| Lead-Free | Yes |
AD7652ASTZRL ピン構成
| ピン 1 | REFIN/REFOUT — Internal 2.5 V reference I/O - connect 0.1 uF cap here |
| ピン 2 | REFGND — Reference ground |
| ピン 3 | AGND — Analog ground |
| ピン 4 | AVCC — Analog supply 4.75 V to 5.25 V |
| ピン 5 | AIN+ — Positive analog input |
| ピン 6 | AIN- — Negative analog input |
| ピン 7 | AVCC — Analog supply (second pin) |
| ピン 8 | AGND — Analog ground (second pin) |
| ピン 9 | BYTESWAP — Byte swap control for parallel interface |
| ピン 10 | HWR/SDOUT — Hardware read / serial data out |
| ピン 11 | RDC — Read data control |
| ピン 12 | CS — Chip select (active low) |
| ピン 13 | WR/RD — Write/Read control |
| ピン 14 | OB/2C — Output bus / 2's complement select |
| ピン 15 | CONVST — Conversion start (rising edge) |
| ピン 16 | BUSY — Conversion busy flag (active high) |
| ピン 17 | DB0/HBEN — Data bit 0 / high byte enable |
| ピン 18 | DB1 — Data bit 1 |
| ピン 19 | DB2 — Data bit 2 |
| ピン 20 | DB3 — Data bit 3 |
| ピン 21 | DGND — Digital ground |
| ピン 22 | DVCC — Digital supply 2.7 V to 5.25 V |
| ピン 23 | DB4 — Data bit 4 |
| ピン 24 | DB5 — Data bit 5 |
| ピン 25 | DB6 — Data bit 6 |
| ピン 26 | DB7 — Data bit 7 |
| ピン 27 | DB8 — Data bit 8 |
| ピン 28 | DB9 — Data bit 9 |
| ピン 29 | DB10 — Data bit 10 |
| ピン 30 | DB11 — Data bit 11 |
| ピン 31 | DGND — Digital ground (second pin) |
| ピン 32 | DVCC — Digital supply (second pin) |
| ピン 33 | DB12 — Data bit 12 |
| ピン 34 | DB13 — Data bit 13 |
| ピン 35 | DB14 — Data bit 14 |
| ピン 36 | DB15 — Data bit 15 |
| ピン 37 | PWRDN — Power down (active low) |
| ピン 38 | RANGE — Analog input range select |
| ピン 39 | SER/PAR — Serial / Parallel mode select |
| ピン 40 | DGND — Digital ground (third pin) |
| ピン 41 | EXTCLK — External clock input (tie to DVCC for internal) |
| ピン 42 | AVCC — Analog supply (third pin) |
| ピン 43 | AGND — Analog ground (third pin) |
| ピン 44 | REFIN — Reference input (tie to REFOUT or ext ref) |
| ピン 45 | REFGND — Reference ground (second pin) |
| ピン 46 | AGND — Analog ground (fourth pin) |
| ピン 47 | AVCC — Analog supply (fourth pin) |
| ピン 48 | AGND — Analog ground (fifth pin) |
主な用途
AD7652ASTZRL の用途: 7 件s: Industrial PLC Analog Input Module, Motor Control Position and Phase-Current Feedback, Multi-Channel Data Acquisition Board, Medical Instrumentation Front End, Power Quality and Energy Metering, Weigh Scale and Strain-Gauge Digitizer, Process Control Loop Transmitter.
Industrial PLC Analog Input Module
The AD7652ASTZRL is a strong fit for industrial PLC analog input modules that require 16-bit absolute accuracy at moderate sampling rates. Its integrated 2.5 V reference saves a BOM line and the true bipolar-capable analog input stage supports direct connection to ±10 V / ±5 V signals from field transmitters without an external op-amp. The 500 kSPS throughput lets one ADC digitize 8 to 16 multiplexed channels at the typical 10 ms to 100 ms PLC scan rate, while the parallel byte interface gluelessly connects to a 16-bit microcontroller bus. In a 16-slot rack this replaces multiple discrete AD574A-type converters and simplifies the analog front end.
おすすめ
Motor Control Position and Phase-Current Feedback
In three-phase motor-control loops the AD7652ASTZRL's 500 kSPS throughput and deterministic SAR latency allow the control MCU to digitize phase currents, DC-bus voltage, and resolver position on the same sample-and-conversion event aligned to the PWM carrier. The 16-bit resolution supports torque-ripple analysis and direct field-weakening control without external gain calibration. The hardware CONVST pin synchronizes conversion start to the PWM reload event, eliminating software jitter and supporting FOC switching frequencies up to 20 kHz. The ±10 V analog input range directly accepts current-shunt amplifier outputs from common driver ICs.
おすすめ
Multi-Channel Data Acquisition Board
Multi-channel data-acquisition boards use the AD7652ASTZRL as the per-channel digitizer behind a CMOS analog multiplexer. Its 500 kSPS throughput lets one ADC service up to 32 multiplexed channels at 15 kSPS each, well above audio-bandwidth instrumentation needs. The 2.5 V internal reference with low drift simplifies calibration routines, and the parallel interface avoids the timing overhead of SPI when the MCU bus is already configured for memory-mapped I/O. This topology is common in laboratory instrumentation, dynamic signal analyzers, and benchtop multimeter designs where channel count is the limiting factor.
おすすめ
Medical Instrumentation Front End
Medical instrumentation front ends for patient monitoring, ECG, and bedside diagnostic devices use the AD7652ASTZRL for its 16-bit resolution at low power and its deterministic SAR conversion that has no pipeline-delay ambiguity. The integrated 2.5 V reference with 5 ppm/ C typical drift provides the DC stability required for medical-grade calibration retention over years of service. The hardware power-down pin supports battery-powered portable designs where the ADC is duty-cycled between samples. Full IEC 60601-1 compliance remains a system-level qualification and is the integrator's responsibility.
おすすめ
Power Quality and Energy Metering
Power-quality meters and energy-metering front ends deploy the AD7652ASTZRL to digitize mains voltage and current waveforms at 4 kSPS to 32 kSPS per channel. The 16-bit resolution captures harmonic distortion profiles up to the 50th harmonic while the hardware CONVST pin synchronizes multiple ADCs in a three-phase meter to within nanoseconds. The internal reference simplifies calibration over temperature and reduces the bill-of-materials cost of an external ADR03. The result is a class-0.2 revenue-grade meter or a class-A power-quality analyzer in a single 48-pin LQFP footprint.
おすすめ
Weigh Scale and Strain-Gauge Digitizer
High-precision weigh scales and strain-gauge digitizers use the AD7652ASTZRL's 16-bit SAR core to digitize load-cell bridge outputs with very low noise and excellent integral non-linearity. The internal 2.5 V reference acts as the bridge excitation rail when combined with a precision op-amp buffer, simplifying the analog front end. The hardware power-down mode supports battery-operated field-portable scales where duty-cycled conversion reduces average dissipation below 10 mW. The deterministic SAR conversion gives repeatable tare and calibration performance from unit to unit.
おすすめ
Process Control Loop Transmitter
Smart 4-20 mA and fieldbus process transmitters use the AD7652ASTZRL as the digitizer for sensor inputs from pressure, temperature, flow, and level transducers. The 500 kSPS throughput is far above the 4 mA-to-20 mA signal bandwidth, allowing digital linearization, square-root extraction, and PID-loop overlay inside the transmitter microcontroller before the result is retransmitted. The 16-bit resolution over the 0-10 V input range gives effective 0-20 mA resolution of approximately 0.3 microamps at the loop side. The integrated 2.5 V reference supports ratiometric measurement when paired with the bridge sensor.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: AD7652ASTZRL — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | AD7652ASTRL | AD7652ASTZ | AD7652ACPZ | AD7656YSTZ-1 | AD7656BSTZ |
|---|---|---|---|---|---|---|
| Package | 48-pin LQFP | 48-pin LQFP (same) | 48-pin LQFP (same) | 48-lead LFCSP 7x7 mm (different footprint) | 64-pin LQFP (different footprint) | 64-pin LQFP (different footprint) |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 16 bits | 16 bits | 16 bits | 16 bits | 16 bits | 16 bits |
| Sample Rate | 500 kSPS | 500 kSPS | 500 kSPS | 500 kSPS | 250 kSPS | 250 kSPS |
| Number of Channels | 1 | 1 | 1 | 1 | 16 (simultaneous sampling) | 16 (simultaneous sampling) |
| Internal Reference | 2.5 V (on-chip) | 2.5 V (on-chip) | 2.5 V (on-chip) | 2.5 V (on-chip) | 2.5 V (on-chip) | 2.5 V (on-chip) |
| Analog Input Range | 0 to 5 V unipolar / ±10 V with scaling | Same | Same | Same | ±10 V bipolar (per channel, software-configurable) | ±10 V bipolar (per channel, software-configurable) |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
主な差別化要因
- Integrated 2.5 V reference - no external ADR03 needed （vs AD7671 family)
- Higher throughput than the AD7656 family in same-silicon speed-grade （vs AD7656YSTZ-1 / AD7656BSTZ)
- True bipolar-capable analog input eliminates the front-end op-amp （vs AD7265BCPZ-REEL)
設計ノート
The analog input on the AD7652ASTZRL must be driven from a low-impedance source - 20 ohms or less per Analog Devices datasheet - so that the 575 pF of input capacitance settles within the acquisition window. If the source impedance is higher than 50 ohms, the SAR conversion will show gain and distortion errors and the digitized value will be a moving target. Always buffer the input with an op-amp such as AD8021 or AD8251, placed within 10 mm of the AIN+/AIN- pins. Do not insert filter resistors between the buffer and the ADC pins unless the resistor is followed by a wideband op-amp stage.
Use a 4.7 uF ceramic decoupling capacitor on each AVCC pin (pins 4, 7, 42, 47) and a 1 uF ceramic on each DVCC pin (pins 22, 32) placed within 5 mm of the package. Use a 0.1 uF X7R or NP0 bypass in parallel for high-frequency noise. The analog and digital ground planes should be joined at a single star point beneath the exposed die-attach paddle of the LQFP. The REFIN/REFOUT pin needs a 0.1 uF ceramic local decoupler routed with a wide, short trace to REFGND. Estimated: a properly bypassed AD7652 design typically passes -85 dB THD at 1 kHz input.
The CONVST (conversion-start) pin on the AD7652 should be driven by a low-jitter CMOS edge, not by a high-impedance source. Jitter on CONVST translates directly into aperture uncertainty and degrades SNR at high input frequencies - keep CONVST edge transitions faster than 5 ns. If the host MCU or DSP does not guarantee this rise time, buffer CONVST through a 74LVC1G17 or 74LVC2G17 gate. The BUSY signal, which marks the end of the conversion window, can be used to synchronize DMA transfers and should be routed at least 2 mm away from switching DC-DC edges.
In power-down mode the AD7652ASTZRL reduces quiescent draw to single-digit microamps, making it suitable for battery-driven instruments and duty-cycled DAQ boards. The hardware PWRDN pin and the software power-down bit must both be de-asserted for at least 500 microseconds before the next CONVST to allow the internal reference buffer to settle. Estimate: re-acquisition time following a power-down exit is approximately 1 ms when the REFIN decoupling cap is 0.1 uF. If the application requires rapid cycling, leave the part in idle mode rather than power-down to avoid settle time penalty.
Route the parallel data bus DB15:DB0 in matched-length groups (within 5 mm) and keep the bus at least 3 mm away from the analog input traces AIN+ and AIN- on the PCB. Place a continuous ground plane beneath the entire LQFP footprint to control return paths and minimize coupling from digital edges into the analog front end. The BYTESWAP and SER/PAR pins should be tied directly to DVCC or DGND (never left floating) to set the desired interface mode permanently - changing modes mid-stream can corrupt the next sample.
コンプライアンス情報
RoHS compliant per Analog Devices product page; reach compliant per distributor listing. Not AEC-Q100 qualified - for automotive applications consult the Automotive parts selector on analog.com. Halogen-free per datasheet disclosure.
