AD9051BRSRL - 10-Bit 60 MSPS Pipelined ADC | Analog Devices
部品番号: AD9051BRSRL ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $16.46 | $16.46 |
| 10 | $14.85 | $148.50 |
| 100 | $13.2 | $1,320.00 |
| 500 | $11.9 | $5,950.00 |
| 1,000 | $10.5 | $10,500.00 |
AD9051BRSRL 概要
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples a continuous analog input and converts it to a discrete digital code at a defined sample rate. Within the converter taxonomy, the AD9051 falls into the pipeline ADC category - pipelined sub-family - which sits between flash converters (faster but power-hungry) and successive-approximation ADCs (lower power but slower). Pipeline ADCs are the workhorses of mid-bandwidth communications, instrumentation, and imaging systems. The 60 MSPS / 10-bit combination places the AD9051 in the entry-to-mid range of that family, where cost, ENOB, and power efficiency matter more than absolute speed.
Key features include a selectable input bandwidth of 50 MHz or 130 MHz (user-selectable via a logic pin), a single +5 V supply requirement, and a built-in sample-and-hold that eliminates the need for an external front-end T/H. The reference is also internal, which simplifies PCB layout and reduces bill-of-materials cost. Industrial-temperature-range operation (-40 C to +85 C) and SSOP packaging allow the part to be used in dense, surface-mount designs where 28-pin dual-inline footprints are too tall.
The AD9051's pipelined architecture samples on a clock edge, then processes each stage through low-resolution sub-ADCs and DACs, with inter-stage gain and digital error correction. The BiCMOS process allows fast analog sampling with low digital leakage, supporting 9.3 ENOB at 10.3 MHz input; this is more than adequate for video-rate and IF-sampling digitizers. The internal reference is trimmed at the factory, removing the need for an external reference and the associated routing noise.
Typical applications include ultrasound imaging front ends, IF-sampling communication receivers, CCD/imaging camera digitizers, and low-cost instrumentation digitizers. The 50/130 MHz selectable bandwidth makes it equally usable for narrow-band IF strips and wider baseband signals such as composite video. The 250 mW power budget is friendly to fanless medical and industrial enclosures.
When designing with the AD9051, run the encode clock from a low-jitter source and decouple AVDD and DVDD close to the pins. The selectable input bandwidth pin should be tied high or low before conversion begins; glitching this pin during operation can corrupt samples. Drive the analog input through a wideband op-amp with at least 100 MHz gain-bandwidth product for full-Nyquist linearity.
This page combines distributor pricing, drop-in alternative parts, and design notes - a synthesis not found in the standalone AD9051 datasheet.
ドロップイン代替品: AD9051BRSRL — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: AD9051BRSRL （同一形状・フットプリント） — 相違点: Package, Architecture, Packaging, Analog Supply Voltage, Input Type.
クイック比較ツール — 並列比較する代替部品を選択:
AD9051BRSZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AD9051BRS
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AD9051BRSRL-2V
✅ ドロップイン✓ 在庫あり
$10.95 / 個
データシートを見る →AD9051BRSZ-2V
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AD9051BRSRL2V
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AD9051BRSRL 最大定格＆電気的特性
| Number of Bits | 10 |
| サンプリングレート | 60 MSPS |
| Number of Inputs | 1 |
| Architecture | Pipelined |
| Data Interface | Parallel |
| Effective Number of Bits (ENOB) | 9.3 at 10.3 MHz input |
| Total Power | 250 mW at 60 MSPS |
| 電源電圧 | +5 V (single supply) |
| Selectable Input Bandwidth | 50 MHz or 130 MHz |
| On-Chip Track-and-Hold | Yes |
| On-Chip Voltage Reference | Yes |
| パッケージ | 28-SSOP (5.30 mm width) |
| 動作温度範囲 | -40 C to +85 C |
| Process Technology | BiCMOS |
| Packaging | Tape & Reel (TR) |
| 実装タイプ | Surface Mount |
AD9051BRSRL ピン構成
| ピン 1 | VREF — Internal voltage reference (decoupling cap location) |
| ピン 2 | AIN — Analog input |
| ピン 3 | AGND — Analog ground |
| ピン 4 | CDS — Bandwidth select (50/130 MHz) |
| ピン 5 | D0 — Digital output bit 0 (LSB) |
| ピン 6 | D1 — Digital output bit 1 |
| ピン 7 | D2 — Digital output bit 2 |
| ピン 8 | D3 — Digital output bit 3 |
| ピン 9 | D4 — Digital output bit 4 |
| ピン 10 | AGND — Analog ground |
| ピン 11 | DVDD — Digital supply (+5 V) |
| ピン 12 | D5 — Digital output bit 5 |
| ピン 13 | D6 — Digital output bit 6 |
| ピン 14 | D7 — Digital output bit 7 |
| ピン 15 | D8 — Digital output bit 8 |
| ピン 16 | D9 — Digital output bit 9 (MSB) |
| ピン 17 | DGND — Digital ground |
| ピン 18 | NC — Not connected (per datasheet) |
| ピン 19 | NC — Not connected (per datasheet) |
| ピン 20 | NC — Not connected (per datasheet) |
| ピン 21 | DRVDD — Output driver supply |
| ピン 22 | ENCODE — Encode clock input (complementary) |
| ピン 23 | ENCODE — Encode clock input |
| ピン 24 | AGND — Analog ground |
| ピン 25 | AVDD — Analog supply (+5 V) |
主な用途
AD9051BRSRL の用途: 6 件s: Ultrasound Imaging Front-End Digitizer, IF-Sampling Communications Receiver, CCD/Camera Imaging Digitizer, Portable Instrumentation Digitizer, Low-Cost Industrial Process Digitizer, Radar/Phase-Array IF Digitizer.
Ultrasound Imaging Front-End Digitizer
The AD9051BRSRL's 60 MSPS sampling rate and 9.3 ENOB at 10.3 MHz make it well suited for digitizing the IF output of an ultrasound receive channel, where mid-bandwidth signal capture around 5-15 MHz dominates. Its integrated T/H eliminates the need for an external sample-and-hold, keeping the front-end footprint small - critical for arrays with hundreds of channels. The 250 mW power budget per channel helps manage thermal density in the probe housing. Compared with a 50 MSPS alternative, the AD9051BRSRL leaves more bandwidth headroom for harmonic imaging modes and Doppler processing, and the +5 V single supply simplifies the high-voltage-to-low-voltage isolation power tree.
おすすめ
IF-Sampling Communications Receiver
For narrow-band IF digitizers in digital radios and software-defined radios (SDR), the AD9051BRSRL's selectable 50 MHz input bandwidth is a clean match for typical intermediate frequencies of 10-45 MHz. At 60 MSPS the converter provides >1.0x oversampling for bandwidths up to 25 MHz, allowing downstream digital filtering to relax channel-filter requirements. The integrated voltage reference removes the cost of an external ADC reference and associated decoupling, while the 28-SSOP package fits dense receiver cards. The pipelined architecture handles sampled IF cleanly without the missing-codes problem of older SAR ADCs in this frequency range, giving SNR performance close to theoretical for 10-bit IF conversion.
おすすめ
CCD/Camera Imaging Digitizer
Industrial CCD cameras and line-scan imagers producing composite-video or RGB parallel streams benefit from the AD9051BRSRL's 130 MHz selectable input bandwidth, which captures wide baseband signals without anti-aliasing complexity. The 60 MSPS rate suits NTSC/PAL digitizers and standard-definition progressive-scan rates, while the 10-bit depth preserves 1024 grayscale or per-channel color levels for machine-vision metrology. The internal T/H and reference keep the BOM small - critical for camera head boards where board area and thermal dissipation are constrained. The +5 V single supply integrates easily with the camera's existing analog rail, and the 28-SSOP fits behind a C-mount envelope.
おすすめ
Portable Instrumentation Digitizer
Handheld oscilloscope-style instruments, bench-top data loggers, and portable vibration analyzers favor the AD9051BRSRL's 60 MSPS / 10-bit combination as a cost-effective single-shot digitizer for signals up to 25 MHz. The 250 mW dissipation allows sealed battery-powered enclosures without active cooling, and the +5 V supply draws from a single Li-ion boost converter rail. The pipelined architecture gives one-shot capture capability within the converter's 60 MSPS window, suitable for transient-recorder front ends. Industrial temperature range (-40 C to +85 C) supports both outdoor field-service instruments and factory-floor installations without part selection splits.
おすすめ
Low-Cost Industrial Process Digitizer
Modbus-style industrial controllers and PLC analog-input modules use the AD9051BRSRL to convert 4-20 mA conditioned signals at rates far below Nyquist, with the 50 MHz input bandwidth setting filtering out conducted EMI from motor inverters and relay switching. Although 60 MSPS is far above process-control needs, the device's pipelined architecture and BiCMOS construction give excellent linearity at lower sample rates, and the 28-SSOP footprint fits alongside many isolated digital I/O. The +5 V supply matches common 24 V-to-5 V DC-DC brick rails, simplifying power tree. Internal reference simplifies calibration - no external precision reference inventory in production.
おすすめ
Radar/Phase-Array IF Digitizer
Secondary surveillance radar (SSR) and IFF transponder receivers use the AD9051BRSRL to digitize 60 MHz IF strips, taking advantage of the converter's 60 MSPS rate to capture the full IF spectrum without aliasing. The selectable 50 MHz input bandwidth can be tuned to the precise transponder response band, rejecting adjacent interrogation signals. The internal T/H and reference reduce part count in dense antenna electronics where each gram of BOM counts. Military variant parts (AD9051BRSRL-2V) can be specified in flight-qualified versions of the same design, maintaining a single PCB layout across commercial and defense product lines.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: AD9051BRSRL — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | AD9051BRSZ | AD9051BRS | AD9051BRSRL-2V | AD9051BRSZ-2V | AD9051BRSRL2V |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 28-SSOP | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Sampling Rate | 60 MSPS | 60 MSPS | 60 MSPS | 60 MSPS | 60 MSPS | 60 MSPS |
| ENOB at 10 MHz | 9.3 bits | 9.3 bits | 9.3 bits | 9.3 bits | 9.3 bits | 9.3 bits |
| Total Power | 250 mW | 250 mW | 250 mW | 250 mW | 250 mW | 250 mW |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C (MIL-PRF screened) | -40 C to +85 C (MIL-PRF screened) | -40 C to +85 C (MIL-PRF screened) |
| Packaging | Tape & Reel (TR) | Tube | Bulk | Tape & Reel (TR) | Tube | Tape & Reel (TR) |
主な差別化要因
- Integrated T/H and reference eliminate external components （vs ADS823 (TI 10-bit 50 MSPS ADC))
- 20 % higher sample rate than same-tier alternatives （vs ADS823 (50 MSPS, 28-SSOP))
- Selectable 50 / 130 MHz input bandwidth for tuning to signal class （vs Generic AD9051 non-selectable footprint variants)
設計ノート
The AD9051BRSRL requires a clean +5 V supply for both AVDD (analog) and DVDD (digital). Per the Analog Devices datasheet, place a 0.1 uF ceramic bypass capacitor within 3 mm of the AVDD pin and a 10 uF tantalum or ceramic bulk capacitor nearby; repeat the same network on the DVDD pin. The pinout separates AGND and DGND returns - connect them to a single ground plane tied at one point under the part. Estimated: assuming AVDD draws 100 mA peak at 60 MSPS, a ferrite bead in series with the AVDD ferrite reduces switching-noise coupling from upstream digital regulators by approximately 10 dB.
Route the encode (sample-clock) lines as a matched differential pair (pins 22 and 23) and keep their length matched to within 1 mm; skew between the true and complementary clock directly reduces SNR. The analog input must be driven by a wideband op-amp with gain-bandwidth product at least 5x the maximum input frequency - the AD8058 or AD797 are commonly paired with this ADC per the datasheet typical applications. Place the driver amplifier within 5 mm of the AIN pin to minimize capacitive loading that would otherwise decrease input bandwidth below the 130 MHz selection.
Use a 4-layer PCB with one continuous ground plane for the AD9051BRSRL; SSOP-28 lead pitch is 0.65 mm, so use 4-mil traces and 4-mil spaces inside the part's escape region. Keep parallel digital output bus traces short (less than 25 mm) and route them over the ground plane rather than across power islands, since the parallel bus can switch 10+ edges per clock and inject noise into AVDD if not properly shielded. The exposed pad on the SSOP is not used; pin 27 (DGND) and pin 25 (AGND) must both be tied to the ground plane with multiple vias.
Do not leave the bandwidth-select pin (BWSEL) floating - the AD9051BRSRL does not have an internal pull-up or pull-down on this pin, per Analog Devices documentation. Tie it high (130 MHz full bandwidth) or low (50 MHz limited bandwidth) before the encoder clock stabilizes; toggling BWSEL during sampling produces large DC level shifts at the input that corrupt multiple sample windows. Avoid using a switching regulator to generate AVDD directly; the converter's 9.3 ENOB is sensitive to supply ripple. Estimated: every 10 mVpp of supply ripple above 1 MHz typically costs 0.2 ENOB bits.
コンプライアンス情報
RoHS and lead-free per Analog Devices product page. No AEC-Q100 qualification claimed - this is an industrial/consumer part; for automotive ADCs, choose ADI's AEC-Q100 qualified families. The -2V suffix parts are not AEC-Q100 qualified either; they are MIL-PRF-38534 screened.
