AD9237BCPZ-65 - 12-Bit, 65 MSPS, 3V Low-Power ADC | Analog Devices
部品番号: AD9237BCPZ-65 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $13.39 | $13.39 |
| 10 | $12.05 | $120.50 |
| 100 | $10.71 | $1,071.00 |
| 500 | $9.37 | $4,685.00 |
| 1,000 | $8.04 | $8,040.00 |
AD9237BCPZ-65 概要
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts a continuous-time, continuous-amplitude analog waveform into a discrete-time, discrete-amplitude digital word. In the product taxonomy, the AD9237BCPZ-65 sits under ADC > data converter > mixed-signal IC > semiconductor. Pipeline ADCs such as this use a cascaded switched-capacitor architecture with a back-end digital correction block to reach sample rates from tens to hundreds of MSPS while dissipating far less power than full-flash converters - the converter IC is therefore a power-management-adjacent subsystem that sits between analog signal-conditioning circuitry and an FPGA, DSP, or dedicated clock-and-timing block in the broader signal chain.
Key specifications include 12-bit resolution, 65 MSPS maximum sample rate, 69 dB SNR (typical at 65 MSPS with 2 V p-p input), 80 dBc SFDR, an internal 1.0 V reference (with optional external reference drive), and a 3 V analog supply (AVDD) plus a 2.5 V driver supply (DRVDD). The 32-pin LFCSP-WQ exposes the analog inputs, clock input, data outputs, and reference pins, while an exposed die paddle provides a low-theta thermal path required for sustained full-rate operation without derating.
Pipeline architecture with 5-bit-per-stage residue gain supports 65 MSPS throughput while keeping per-sample latency low; the digital output stage is synchronized to the rising or falling input clock edge and can drive a 2.5 V CMOS bus into an FPGA capture stage. The proprietary SHA maintains > 250 MHz input bandwidth, enabling IF undersampling of carriers up to about 100 MHz.
Typical applications include medical ultrasound imaging receivers, communications IF sampling (GSM/EDGE/UMTS baseband), portable instrumentation and data acquisition, and digital oscilloscope front ends. Its wide input bandwidth also supports CCD/CIS imaging and consumer video digitizers in the 20-65 MSPS class.
Designers should follow the recommended layout pattern of separating AVDD/DRVDD planes and routing differential analog inputs as a 100 ohm matched pair into the ADC. The exposed paddle must be soldered to a low-impedance ground pour to keep junction rise below the 125 C operating limit; failure to do this is the most common cause of field failures in 65 MSPS pipeline ADCs. This page synthesizes verified distributor pricing, drop-in same-package alternatives, and design guidance not aggregated on any single manufacturer or distributor page.
ドロップイン代替品: AD9237BCPZ-65 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: AD9237BCPZ-65 （同一形状・フットプリント） — 相違点: Architecture, Package, Input Type, Analog Input Type, Analog Supply Voltage (AVDD).
クイック比較ツール — 並列比較する代替部品を選択:
AD9237BCPZ-40
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AD9237BCPZ-20
✅ ドロップイン✓ 在庫あり
$9.85 / 個
データシートを見る →AD9051BRSRL-2V
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$10.95 / 個
データシートを見る →AD9235BRUZ-65
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
AD9235BCPZ-65
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
AD9237BCPZ-65 最大定格＆電気的特性
| 分解能 | 12 bits |
| Sample Rate (Max) | 65 MSPS |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Analog Supply Voltage (AVDD) | 2.7 V to 3.6 V (3 V nominal) |
| Driver Supply Voltage (DRVDD) | 2.25 V to 3.6 V (2.5 V nominal) |
| Power Dissipation (Typical) | 200 mW at 65 MSPS |
| Analog Input Type | Differential, 2 V p-p full-scale |
| SNR (Typical, 65 MSPS) | 69 dB |
| SFDR (Typical) | 80 dBc |
| 基準電圧 | 1.0 V internal (external drive optional) |
| Input Bandwidth | 250 MHz (typ) |
| Digital Output Interface | 12-bit parallel CMOS/TTL |
| 動作温度範囲 | -40 C to +85 C |
| パッケージ | 32-LFCSP-WQ (5 mm x 5 mm) with exposed pad |
| 実装タイプ | Surface Mount |
| MSLレベル | 3 |
| RoHS ステータス | Compliant |
AD9237BCPZ-65 ピン構成
| ピン 1 | AIN — Analog input (true) |
| ピン 2 | AINB — Complementary analog input |
| ピン 3 | VREF — Voltage reference input/output, 1.0 V nominal |
| ピン 4 | REFT — Reference decoupling top |
| ピン 5 | REFB — Reference decoupling bottom |
| ピン 6 | CML — Common-mode level output for analog input biasing |
| ピン 7 | AVDD — 3 V analog supply |
| ピン 8 | AGND — Analog ground |
| ピン 9 | AVDD — 3 V analog supply |
| ピン 10 | AGND — Analog ground |
| ピン 11 | DRVDD — 2.5 V digital output driver supply |
| ピン 12 | DRGND — Digital ground |
| ピン 13 | CLK — Clock input (true) |
| ピン 14 | CLKB — Complementary clock input |
| ピン 15 | OTR — Out-of-range indicator |
| ピン 16 | D11 — Digital output bit 11 (MSB) |
| ピン 17 | D10 — Digital output bit 10 |
| ピン 18 | D9 — Digital output bit 9 |
| ピン 19 | D8 — Digital output bit 8 |
| ピン 20 | D7 — Digital output bit 7 |
| ピン 21 | D6 — Digital output bit 6 |
| ピン 22 | D5 — Digital output bit 5 |
| ピン 23 | D4 — Digital output bit 4 |
| ピン 24 | D3 — Digital output bit 3 |
| ピン 25 | D2 — Digital output bit 2 |
| ピン 26 | D1 — Digital output bit 1 |
| ピン 27 | D0 — Digital output bit 0 (LSB) |
| ピン 28 | DRVDD — 2.5 V digital driver supply |
| ピン 29 | DRGND — Digital ground |
| ピン 30 | AGND — Analog ground |
| ピン 31 | AVDD — 3 V analog supply |
| ピン 32 | AGND — Analog ground / exposed pad tie |
主な用途
AD9237BCPZ-65 の用途: 6 件s: Medical Ultrasound Receiver Front End, Communications IF Sampling / GSM-EDGE Baseband, Portable Instrumentation and Data Acquisition, Digital Oscilloscope Front End, CCD/CIS Imager Digitizer, Industrial Process Control Input Module.
Medical Ultrasound Receiver Front End
The AD9237BCPZ-65 fits ultrasound receivers because its 250 MHz analog input bandwidth captures 5-10 MHz band-limited transducer return signals cleanly while the 65 MSPS sample rate provides the headroom required for 4x to 8x oversampling of the 2-10 MHz IF. Its 12-bit resolution (69 dB SNR) yields dynamic range sufficient for 40 dB echo return plus 30 dB headroom, while the pipelined core keeps per-beam latency low for real-time scanning arrays.
おすすめ
Communications IF Sampling / GSM-EDGE Baseband
For cellular base-station IF stages, the AD9237BCPZ-65's wide 250 MHz input bandwidth supports IF undersampling of carriers up to ~100 MHz, eliminating a downconversion mixer stage and reducing BOM cost. The 65 MSPS throughput captures 3.84 MHz UMTS chips while leaving sufficient margin for the antialiasing filter transition band. The 80 dBc SFDR preserves ACPR for the four-carrier GSM linearization envelope.
おすすめ
Portable Instrumentation and Data Acquisition
With ~200 mW typical dissipation from a single 3 V rail, the AD9237BCPZ-65 is well-suited for battery-powered data-acquisition modules that need 12-bit precision at 65 MSPS without inducing thermal derating. Its internal 1.0 V reference simplifies external circuitry, and the 32-LFCSP-WQ 5x5 footprint keeps the analog section under 25 mm² of board area, an important constraint in portable test equipment.
おすすめ
Digital Oscilloscope Front End
Oscilloscope input stages benefit from the AD9237BCPZ-65's pipelined 12-bit architecture and 65 MSPS throughput for 50-100 MHz bandwidth mid-range scopes. The wide input bandwidth can capture clock edges and harmonics well beyond Nyquist, while 80 dBc SFDR delivers truthful harmonic-distortion displays on signals up to full-scale. The LFCSP-WQ exposed pad yields a small outline with the thermal performance needed for continuous full-rate sampling.
おすすめ
CCD/CIS Imager Digitizer
For machine-vision and document scanner digitizers, the AD9237BCPZ-65 provides 65 MSPS throughput that captures 2400-element line-scan cameras at 25 kHz line rate with margin for higher line rates. The differential input pair handles the CCD/CIS output drive with low noise, while the 12-bit output bytes feed directly into an FPGA serializer for image buffering. This converts camera analog signals into 4095-level grayscale words with 69 dB SNR.
おすすめ
Industrial Process Control Input Module
Multi-channel industrial signal processors that aggregate 4-8 sensors per board can use the AD9237BCPZ-65 as the master ADC after multiplexer switching to capture ultrasonic, vibration, or strain-gauge waveforms with 12-bit resolution and 65 MSPS single-shot capability. The 3 V single-rail design isolates digital noise from sensitive analog transducer bridges, while the 32-LFCSP-WQ footprint enables compact single-board modules sealed in IP65 enclosures.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: AD9237BCPZ-65 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | AD9237BCPZ-40 | AD9237BCPZ-20 | AD9051BRSRL-2V | AD9235BCPZ-65 |
|---|---|---|---|---|---|
| Package | 32-LFCSP-WQ (5x5) | 32-LFCSP-WQ (5x5) - same | 32-LFCSP-WQ (5x5) - same | 28-SSOP (verify pin-by-pin) | 32-LFCSP-WQ (5x5) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Maximum Sample Rate | 65 MSPS | 40 MSPS | 20 MSPS | 60 MSPS | 65 MSPS |
| Number of Channels | 1 | 1 | 1 | 1 | 1 |
| Lifecycle Status | Active (Rev. C datasheet) | Active | Active | Active | Active |
主な差別化要因
- 65 MSPS in the smallest LFCSP-WQ 5x5 ADI pipeline family （vs AD9237BCPZ-40)
- Lower cost per MSPS than AD9235 family in same package （vs AD9235BCPZ-65)
- Single 3 V AVDD with internal 1 V reference simplifies power tree （vs AD9051BRSRL-2V)
設計ノート
Estimated: the 32-LFCSP-WQ (5x5) exposed thermal pad has less than 200 um stand-off. Use an array of thermal vias (typically 12 vias 0.3 mm diameter, 1 mm pitch) under the paddle to a 2 oz inner copper ground pour. Without this via stitch, junction temperature can rise above 110 C at full 65 MSPS continuous operation, derating both SNR and long-term reliability. The analog (AGND) and digital (DRGND) grounds should still join only at the package pin and via pad - never run a continuous ground plane split that loops around the analog inputs.
Place a 0.1 uF X7R decoupling capacitor within 2 mm of each AVDD pin and a 10 uF tantalum/ceramic bulk capacitor on the supply side. AVDD noise above 1 mV p-p directly couples into the SHA and degrades SNR; expect up to 2 dB SNR loss for each additional 10 mV of AVDD ripple. The 2.5 V DRVDD rail should be similarly decoupled to prevent CMOS-output transient ground bounce from feeding back into the analog ground reference via the package substrate.
Route the differential analog inputs AIN/AINB as a 100 ohm matched differential pair with constant spacing across the entire path; a discontinuity or stub within 10 mm of the analog input pins will create a reflection that becomes a sparkle code error in the ADC output. The clock pair CLK/CLKB must also be routed as a 100 ohm differential pair from a low-jitter clock source; clock jitter budget at 65 MSPS for 70 dB SNR is approximately 0.5 ps-rms. Treat AIN, AINB, CLK, CLKB as a matched quadrature group with no via transitions except where absolutely required.
Do not oversample beyond 65 MSPS by overclocking the AD9237BCPZ-65 - the digital correction block will fail to maintain bit weighting and SNR collapses above the rated maximum sample rate. Do not drive AIN alone with a single-ended 2 V p-p source: the part expects 2 V p-p differential, so connect one of AIN/AINB to the inverted version of the other, not to ground. Finally, do not leave REFT/REFB unbypassed; both need 0.1 uF X7R ceramics to AGND, otherwise the internal reference amplifier will oscillate and corrupt the SHA bias level.
コンプライアンス情報
RoHS and REACH compliance per Analog Devices product family declaration. Lead-free finish confirmed by 'Z' in ordering code (BCPZ). Halogen-free status not explicitly stated in the AD9237 datasheet; flagged as unknown rather than assumed.
