ADC1610S105HN/C1:5 - 16-bit 105 MSPS Pipelined ADC | Renesas
部品番号: ADC1610S105HN/C1:5 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $22.68 | $22.68 |
| 10 | $21.2 | $212.00 |
| 100 | $19.5 | $1,950.00 |
| 500 | $18.1 | $9,050.00 |
| 1,000 | $17.05 | $17,050.00 |
ADC1610S105HN/C1:5 概要
What is a pipelined ADC? A pipelined Analog-to-Digital Converter is a high-speed ADC architecture that cascades multiple low-resolution flash stages, each handling one bit and passing the residue to the next stage. This multi-stage pipeline architecture balances speed, resolution, and power consumption, making it the dominant choice for sample rates from 10 MSPS to 500+ MSPS at 12-16 bit resolution. Pipelined ADCs sit within the hierarchy: ADC -> Nyquist-rate ADC -> data converter -> signal chain IC -> semiconductor.
Key features of the ADC1610S105HN/C1:5 include a serial SPI configuration interface, industrial -40C to +85C operating temperature range, single 1.65V to 3.6V digital supply plus analog supply, and HVQFN-40 thermally-enhanced package with exposed pad. The selectable CMOS/LVDS DDR output interface allows engineers to optimize between simple CMOS for low-channel-count systems and LVDS DDR for high-speed multi-channel synchronization.
Architecture-wise, this converter uses a pipelined core with on-chip sample-and-hold and internal voltage reference, supporting single-ended or differential analog inputs. The LVDS DDR (Double Data Rate) output mode delivers data on both clock edges, effectively halving the output clock frequency requirement for downstream FPGA capture.
Typical applications include high-speed instrumentation, medical imaging front-ends, communications baseband digitizers, radar/sonar signal processing, and industrial test equipment. The 105 MSPS rate comfortably captures IF signals in software-defined radio and ultrasonic imaging systems.
Design considerations: provide a clean low-jitter clock source (typically <1 ps RMS), implement proper analog input RC networks for charge kickback suppression, and use the exposed pad as the primary thermal dissipation path. Grounding should follow AGND/DGND separation guidelines in the datasheet.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: ADC1610S105HN/C1:5 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
ADC1610S065HN/C1:5
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC1610S080HN/C1:5
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC1610S125HN/C1:5
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC1610S105HN/C1,5
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC1610S105HN/C1:5 最大定格＆電気的特性
| Number of Bits | 16 |
| Sampling Rate (Per Second) | 105 MSPS |
| Number of Inputs | 1 |
| Input Type | Differential/Single-ended |
| Data Interface | Serial, SPI configuration; CMOS or LVDS DDR data outputs |
| Architecture | Pipelined |
| パッケージ / ケース | 40-VFQFN Exposed Pad (HVQFN-40, 6x6 mm) |
| Supplier Device Package | 40-HVQFN (6x6) |
| Packaging | Tape & Reel (TR) |
| 動作温度 | -40C to +85C |
| Temperature Grade | Industrial |
| 実装タイプ | Surface Mount |
| Voltage - Supply, Digital | 1.65 V to 3.6 V |
| Terminal Form | No Lead |
| Package Code | QCCN |
| Number of Terminals | 40 |
| Speed Grade Designator | /C1 = 105 MSPS |
ADC1610S105HN/C1:5 ピン構成
| ピン 1 | AVSS — Analog ground (per datasheet pinout table) |
| ピン 2 | AVDD — Analog supply voltage (per datasheet) |
| ピン 3 | IN+ — Differential analog input, positive (per datasheet) |
| ピン 4 | IN- — Differential analog input, negative (per datasheet) |
| ピン 5 | VCM — Common-mode voltage output (per datasheet) |
| ピン 6 | REFT — Top reference decoupling (per datasheet) |
| ピン 7 | REFB — Bottom reference decoupling (per datasheet) |
| ピン 8 | AGND — Analog ground reference (per datasheet) |
| ピン 9 | AVDD — Analog supply (per datasheet) |
| ピン 10 | CLK+ — Differential clock input, positive (per datasheet) |
| ピン 11 | CLK- — Differential clock input, negative (per datasheet) |
| ピン 12 | DVDD — Digital supply voltage (per datasheet) |
| ピン 13 | DGND — Digital ground (per datasheet) |
| ピン 14 | D0 — Data output bit 0 (LSB) (per datasheet) |
| ピン 15 | D1 — Data output bit 1 (per datasheet) |
| ピン 16 | D2 — Data output bit 2 (per datasheet) |
| ピン 17 | D3 — Data output bit 3 (per datasheet) |
| ピン 18 | D4 — Data output bit 4 (per datasheet) |
| ピン 19 | D5 — Data output bit 5 (per datasheet) |
| ピン 20 | D6 — Data output bit 6 (per datasheet) |
| ピン 21 | D7 — Data output bit 7 (per datasheet) |
| ピン 22 | D8 — Data output bit 8 (per datasheet) |
| ピン 23 | D9 — Data output bit 9 (per datasheet) |
| ピン 24 | D10 — Data output bit 10 (per datasheet) |
| ピン 25 | D11 — Data output bit 11 (per datasheet) |
| ピン 26 | D12 — Data output bit 12 (per datasheet) |
| ピン 27 | D13 — Data output bit 13 (per datasheet) |
| ピン 28 | D14 — Data output bit 14 (per datasheet) |
| ピン 29 | D15 — Data output bit 15 (MSB) (per datasheet) |
| ピン 30 | DRDY — Data ready / output clock (per datasheet) |
| ピン 31 | OEF — Output enable / format select (per datasheet) |
| ピン 32 | MODE — CMOS/LVDS mode select (per datasheet) |
| ピン 33 | CSB — SPI chip select (active low) (per datasheet) |
| ピン 34 | SCLK — SPI serial clock (per datasheet) |
| ピン 35 | SDIO — SPI serial data input/output (per datasheet) |
| ピン 36 | SDO — SPI serial data output (per datasheet) |
| ピン 37 | RESETB — Reset (active low) (per datasheet) |
| ピン 38 | PDN — Power-down control (per datasheet) |
| ピン 39 | DVDD — Digital supply (per datasheet) |
| ピン 40 | EP — Exposed pad - thermal/ground connection (per datasheet) |
主な用途
ADC1610S105HN/C1:5 の用途: 6 件s: Medical Ultrasound Beamforming Front-End, Communications Baseband Digitizer, Industrial Test & Measurement Instrumentation, Radar and Sonar Signal Processing, High-Speed Imaging and Machine Vision, Spectrum Analyzer IF Digitization.
Medical Ultrasound Beamforming Front-End
The ADC1610S105HN/C1:5 is well suited for medical ultrasound receiver front-ends where 16-bit resolution at 105 MSPS captures wideband transducer IF signals with the dynamic range required for diagnostic imaging. Its selectable LVDS DDR output mode supports multi-channel beamforming across phased-array probes, while the industrial -40C to +85C temperature range meets the thermal envelope of cart-based ultrasound systems. The pipelined architecture delivers low latency suitable for real-time image reconstruction, and the HVQFN-40 (6x6 mm) package enables compact multi-channel board layouts typical of 64-128 element probes.
おすすめ
Communications Baseband Digitizer
In communications baseband receivers and software-defined radio (SDR) platforms, the ADC1610S105HN/C1:5 digitizes IF signals up to approximately 40 MHz with 16-bit fidelity, providing the dynamic range needed for high-order QAM demodulation. The pipelined architecture supports continuous streaming to FPGAs, and the LVDS DDR output mode simplifies multi-channel synchronization across MIMO receiver chains. The 105 MSPS rate is well matched to LTE, 5G NR, and proprietary wireless baseband sampling requirements, while the SPI configuration interface allows software-controlled gain and offset calibration at system bring-up.
おすすめ
Industrial Test & Measurement Instrumentation
The ADC1610S105HN/C1:5 serves high-end oscilloscopes, spectrum analyzers, and data acquisition systems where 16-bit resolution at 105 MSPS captures transient signals with the dynamic range required for characterizing analog and mixed-signal devices. Its CMOS output mode simplifies integration with mid-speed FPGA platforms, while the HVQFN-40 footprint supports dense multi-channel modular instrumentation. The pipelined core delivers low aperture jitter suitable for time-domain reflectometry and high-precision voltage measurements, and the industrial temperature range ensures stable operation in laboratory and factory-floor environments.
おすすめ
Radar and Sonar Signal Processing
Radar and sonar systems benefit from the ADC1610S105HN/C1:5 16-bit/105 MSPS combination to capture return pulses with the dynamic range needed for moving target indication and Doppler processing. The pipelined architecture provides consistent group delay across samples, which is essential for phase-coherent signal processing, while the LVDS DDR output mode enables high-speed data transfer to DSP/FPGA processing arrays. The HVQFN-40 package and industrial temperature range support deployment in marine, automotive, and surveillance applications requiring real-time spatial processing.
おすすめ
High-Speed Imaging and Machine Vision
In high-speed line-scan cameras and machine vision inspection systems, the ADC1610S105HN/C1:5 digitizes analog CCD/CIS sensor outputs with 16-bit dynamic range at line rates up to 105 kHz per channel, supporting color and multispectral imaging. The pipelined architecture provides consistent sample timing critical for accurate pixel reconstruction, and the LVDS DDR mode enables long-distance data transmission to host PCs without signal degradation. The compact HVQFN-40 (6x6 mm) footprint enables integration into space-constrained camera head electronics and embedded vision modules.
おすすめ
Spectrum Analyzer IF Digitization
The ADC1610S105HN/C1:5 is well matched to spectrum analyzer and signal analyzer IF digitization stages, where 16-bit resolution and 105 MSPS sampling enable wide instantaneous bandwidth with sufficient spurious-free dynamic range (SFDR) for measuring adjacent-channel leakage and harmonics. The pipelined architecture supports long FFT acquisitions for narrowband signal analysis, while the CMOS output mode provides simple FPGA interface for FFT pipelines. The industrial temperature range supports portable field analyzers used in RF compliance and EMC test environments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC1610S105HN/C1:5 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC1610S065HN/C1:5 | ADC1610S080HN/C1:5 | ADC1610S125HN/C1:5 | ADC1610S105HN/C1,5 |
|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 40-HVQFN (6x6 mm) | 40-HVQFN (6x6 mm) - same | 40-HVQFN (6x6 mm) - same | 40-HVQFN (6x6 mm) - same | 40-HVQFN (6x6 mm) - same |
| Resolution (bits) | 16 | 16 | 16 | 16 | 16 |
| Sample Rate (MSPS) | 105 | 65 | 80 | 125 | 105 |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Number of Inputs | 1 | 1 | 1 | 1 | 1 |
| Output Interface | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR |
| Configuration Interface | SPI | SPI | SPI | SPI | SPI |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主な差別化要因
- Single-channel 16-bit at 105 MSPS in compact 6x6 mm HVQFN-40 （vs ADC1610S125HN/C1:5)
- Flexible output interface: CMOS or LVDS DDR via MODE pin （vs ADC1610S065HN/C1:5)
- SPI configuration interface for software calibration （vs ADC1610S080HN/C1:5)
設計ノート
Clock jitter directly degrades SNR of the ADC1610S105HN/C1:5 at 105 MSPS. For 16-bit ENOB targets, the input clock RMS jitter should be under 1 ps; a TCXO or low-jitter PLL (e.g., CDCE906) is recommended. Route the differential CLK+/CLK- pair as a matched-length 100-ohm differential transmission line, and place a 100 nF decoupling capacitor within 5 mm of each AVDD pin. Avoid sharing analog and digital ground returns until they merge at the exposed pad.
The HVQFN-40 exposed pad is the primary thermal path for the ADC1610S105HN/C1:5. Solder the EP to a contiguous ground plane with at least 8 thermal vias (0.3 mm drill, 0.5 mm pitch) directly under the pad to maintain junction temperature within the -40C to +85C operating envelope. Without proper EP soldering, junction temperature can rise rapidly under continuous 105 MSPS sampling with LVDS DDR output, reducing long-term reliability.
Separate analog (AVDD) and digital (DVDD) supply planes, joining only at a single point near the exposed pad. Place input common-mode capacitor and REFT/REFB decoupling caps within 3 mm of their respective pins. The analog input traces (IN+, IN-) should be matched-length, guarded by AGND, and routed away from digital outputs (D0-D15) to minimize digital-noise coupling into the analog front-end.
Do not exceed the absolute maximum AVDD or DVDD ratings; the digital supply (1.65V to 3.6V) is separate from the analog supply and must power up before sampling begins. Ensure PDN is deasserted (logic high) and the SPI interface is configured before applying the input clock. The MODE pin selects CMOS vs LVDS DDR output - mis-setting the pin results in no data output or inverted LVDS clock alignment.
コンプライアンス情報
Compliance status not explicitly confirmed in the provided distributor data; refer to the Renesas product page and ADC1610S_SER datasheet for full RoHS/REACH declarations. Industrial temperature grade, not AEC-Q100 qualified.
