ADF4112BRU - 3 GHz Integer-N PLL | Analog Devices
部品番号: ADF4112BRU ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $3.55 | $3.55 |
| 10 | $3.55 | $35.50 |
| 100 | $3.55 | $355.00 |
| 500 | $3.55 | $1,775.00 |
| 1,000 | $3.55 | $3,550.00 |
ADF4112BRU 概要
A PLL frequency synthesizer is a clock-and-timing integrated circuit that locks an output oscillator to a stable reference frequency. Within the power-management and signal-chain hierarchy, the ADF4112 belongs to the frequency-synthesizer class, where the phase detector, charge pump, counters, prescaler, and voltage-controlled oscillator work as a closed feedback loop. Its integer-N architecture simplifies programming because the feedback division ratio is formed from integer counters rather than a fractional divider.
The verified product information identifies a 3 GHz maximum PLL operating frequency, a 5.5 V supply, a separate charge-pump supply, programmable reference and counter functions, and programmable charge-pump currents. The 16-TSSOP package provides a compact surface-mount footprint suitable for RF boards, instrumentation, communications equipment, and test-and-measurement systems. The manufacturer product page lists the part as production and provides a starting list price of $3.55.
In operation, the reference signal passes through the programmable reference divider, while the feedback path uses the prescaler and A/B counters. The phase-frequency detector compares the divided reference and feedback signals, and the charge pump converts the phase error into a tuning voltage for the external voltage-controlled oscillator. A separate charge-pump supply permits extended tuning voltage, while programmable current helps tune loop dynamics.
Typical applications include wireless receiver and transmitter local oscillators, RF upconversion and downconversion stages, instrumentation, and communications test equipment. Because the target is an integer-N device, designs needing fractional-N synthesis may require a different part. This page combines verified manufacturer and distributor information with practical configuration guidance, helping engineers distinguish function from package and evaluate replacement constraints.
Designers should verify the complete datasheet for counter widths, prescaler options, reference-input limits, output-driver configuration, loop-filter requirements, and exposed thermal behavior before layout. The reference and feedback paths require careful RF routing, while the charge-pump and loop-filter components must be placed close to the relevant pins to minimize noise and phase error. Pricing shown in this record reflects the manufacturer listing available as of 2026-10-23.
ドロップイン代替品: ADF4112BRU — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
ADF4110BRUZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADF4156BRUZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADF4112BRUZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADF4112BRU 仕様
| Device Type | Integer-N PLL frequency synthesizer |
| Maximum PLL Frequency | 3.0 GHz |
| Power Supply | 5.5 V |
| Charge Pump Supply | Separate VP supply |
| Prescaler | Programmable dual-modulus P/P+1 prescaler |
| Phase Detector | Low-noise digital phase-frequency detector |
| Charge Pump | Precision charge pump with programmable current |
| Reference Divider | Programmable |
| A Counter | Programmable 6-bit counter |
| B Counter | Programmable 13-bit counter |
| Architecture | Integer-N |
| パッケージ | 16-lead TSSOP, 4.40 mm width |
| 実装タイプ | Surface mount |
| Tuning Voltage | Extended tuning voltage supported by separate charge-pump supply |
| Manufacturer List Price | $3.55 starting price as of 2026-10-23 |
ADF4112BRU 16-lead tssop, 4.40 mm width ピン配置ガイド
ADF4112BRU (16-lead tssop, 4.40 mm width パッケージ) のピン配置。 ピン番号、機能、接続図はメーカーのデータシートで定義されています。正確なフットプリントとはんだ付けのガイドラインについては、データシートを参照してください。
詳細なピン配置データはありません: ADF4112BRU.
詳細は データシート をご参照ください。
主な用途
ADF4112BRU の用途: 6 件s: Wireless Transmitter Local Oscillator, Wireless Receiver Downconversion, RF Communications Test Equipment, RF Instrumentation and Measurement, Frequency Conversion in RF Modules, Industrial RF Control and Monitoring.
Wireless Transmitter Local Oscillator
The ADF4112BRU fits a programmable transmitter local oscillator because its 3.0 GHz maximum PLL frequency provides headroom for common RF conversion stages and its programmable prescaler and counters permit integer-N feedback division. Place the synthesizer in the feedback path of an external voltage-controlled oscillator, use the reference divider to establish the comparison rate, and tune the charge pump and loop filter for the required lock time and phase noise. The key benefit is repeatable frequency setting from a stable reference. The main design trade-off is that integer-N division does not directly provide fractional-N channel spacing, so the reference plan and permitted spur performance must be evaluated before schematic release.
おすすめ
Wireless Receiver Downconversion
The ADF4112BRU can generate the local oscillator used to downconvert a received RF signal. Its 3.0 GHz maximum operating frequency, programmable dual-modulus prescaler, and programmable A and B counters support flexible integer-N feedback ratios from a stable reference. Place the PLL around the receiver VCO and use a passive or active loop filter selected from the required bandwidth, phase-noise target, and VCO gain. This approach simplifies channel-frequency programming compared with a fixed oscillator. Engineering attention is still required because reference spurs and loop-filter components can dominate close-in phase noise, and the complete datasheet must confirm the selected prescaler covers the intended channel plan.
おすすめ
RF Communications Test Equipment
For laboratory or production test equipment, the ADF4112BRU can provide a programmable RF reference for exercising receivers, transmitters, and frequency-conversion assemblies. Its 3.0 GHz capability and integer-N divider architecture support repeatable tone and LO generation, while the separate charge-pump supply extends the tuning-voltage range available to the external VCO. A practical implementation should synchronize the synthesizer to a low-phase-noise reference, isolate the loop filter from the RF section, and characterize settling time before automating measurements. Compared with a simple fixed oscillator, this arrangement broadens test-frequency coverage, although fractional-N hardware may be preferable when very fine frequency steps are essential.
おすすめ
RF Instrumentation and Measurement
The ADF4112BRU is suitable for RF instrumentation that requires a digitally controlled oscillator rather than a fixed-frequency source. By referencing the PLL to a stable clock, an instrument can set local-oscillator frequencies across the ADF4112's 3.0 GHz maximum range using the programmable prescaler, A counter, B counter, and reference divider. The synthesizer can be paired with an external VCO to set the required RF output level and tuning range. Designers should optimize the loop for phase noise and settling time, use short RF feedback routes, and keep switching regulators away from sensitive reference and charge-pump nodes. The benefit is repeatable, software-defined RF excitation across multiple test channels.
おすすめ
Frequency Conversion in RF Modules
The ADF4112BRU can support frequency conversion in compact RF modules where upconversion or downconversion requires a programmable local oscillator. Its 16-lead TSSOP package conserves board area, and the integrated divider and charge-pump functions reduce the number of separate digital timing components. Place the device adjacent to the VCO and loop filter, keep the feedback division path compact, and provide filtering on supply and reference inputs. The 3.0 GHz upper limit makes the part suitable for many RF bands, but the exact prescaler range, VCO tuning voltage, and channel spacing must be verified. Integer-N operation is advantageous for simple firmware but less suitable than fractional-N synthesis when fine steps or low deterministic spur levels dominate the specification.
おすすめ
Industrial RF Control and Monitoring
The ADF4112BRU can be used in industrial RF systems that synthesize a local oscillator for sensing, communication, or process-monitoring equipment. Programmable frequency control allows one board design to cover multiple operating frequencies, while the reference-driven PLL provides long-term frequency stability tied to the external reference quality. For industrial environments, isolate the oscillator and synthesizer from motors, relays, and switching supplies, use a controlled reference distribution network, and validate lock performance over the full temperature range. The 3.0 GHz device capability offers useful RF-design headroom, but industrial compliance and EMC requirements must be assessed separately because the supplied data does not establish AEC-Q100 or regulatory qualification.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADF4112BRU — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADF4110BRUZ | ADF4156BRUZ | ADF4112BRUZ |
|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 16-TSSOP (4.40 mm width) | 16-TSSOP (4.40 mm width) | 16-TSSOP (4.40 mm width) | 16-TSSOP (4.40 mm width) |
主な差別化要因
- Higher operating-frequency ceiling in the identified Analog Devices family （vs ADF4110BRUZ)
- Exact 3.0 GHz family function （vs ADF4112BRUZ)
- Clearer selection basis within a related PLL portfolio （vs ADF4156BRUZ)
設計ノート
Place the charge-pump and loop-filter components close to the corresponding ADF4112BRU pins, and keep the external VCO and prescaler feedback path short. The reference input is sensitive to phase noise and spur pickup, so route it away from switching nodes and provide a stable ground return. High-frequency RF feedback traces should use controlled geometry and a continuous reference plane. Before release, compare measured phase noise and lock behavior with a simulation built from the actual VCO gain and loop-filter values.
Treat the 5.5 V main supply and separate charge-pump supply as distinct noise domains. Decouple each rail close to its pins, verify acceptable voltage ranges in the manufacturer datasheet, and avoid routing charge-pump current through narrow or shared supply paths. Because the separate VP supply supports extended tuning voltage, check both the allowed VP value and the external VCO tuning range. Incorrect rail sequencing or inadequate bypassing can cause poor lock performance, charge-pump disturbance, or damage.
Do not assume that every related ADF PLL is a drop-in replacement. ADF4112BRU uses a 3.0 GHz integer-N architecture with a programmable prescaler and counters, while the supplied comparison identifies ADF4110BRUZ as a 550 MHz family member and ADF4156BRUZ as a different PLL family. Validate pin names, serial-register addresses, power rails, VCO interface, and timing against the target device. Changing only the orderable suffix can also alter tape orientation or reel packaging even when electrical parameters match.
コンプライアンス情報
The supplied excerpts identify RoHS and REACH as comparison attributes for related devices but do not provide an explicit compliance declaration for ADF4112BRU. No compliance assumption has been made.
