ADS5220PFBRG4 - 12-Bit 40MSPS 3.3V ADC | Texas Instruments
部品番号: ADS5220PFBRG4 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.05 | $1,405.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $11.05 | $11,050.00 |
ADS5220PFBRG4 概要
A pipelined ADC (Analog-to-Digital Converter) is a high-speed data converter architecture that resolves each input sample through a cascade of low-resolution stage converters, each producing a residue for the next stage. The pipelined architecture sits between successive-approximation-register (SAR) ADCs (low speed, high precision) and flash ADCs (very fast, low resolution), balancing sample rate and resolution. The ADS5220 lineage belongs to TI's high-performance data-converter family used in industrial, medical, and communications systems requiring precise mid-bandwidth digitization up to tens of megasamples per second.
The device features a sample-and-hold (S/H) front end with 1:1 S/H-to-ADC architecture, a parallel CMOS-compatible digital interface, and a wide operating temperature range of -40 °C to +85 °C. An internal reference option simplifies board design, while the programmable input range (via reference scaling) allows scaling to match the dynamic range of the upstream driver amplifier. The 48-TQFP footprint provides a balance between thermal dissipation and board area, suitable for moderate channel-density designs.
Typical applications include ultrasound imaging front ends, portable instrumentation digitizers, digital oscilloscope input stages, communications IF sampling, and CCD image processing. The 195 mW dissipation at 40 MSPS enables deployment in thermally constrained designs without forced-air cooling, while the +3.3V single supply simplifies power-rail design in 3.3V systems.
When designing in the ADS5220PFBRG4, decouple AVDD and DVDD with separate, low-inductance traces and place 0.1 µF ceramic bypass capacitors as close as possible to each supply pin. Drive the analog inputs through a low-noise, low-distortion differential amplifier (such as a THS4503-class driver) to preserve the 70 dB SNR. Observe the datasheet's input common-mode and clock-duty-cycle recommendations to avoid degrading SFDR.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: ADS5220PFBRG4 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADS5220PFBRG4 （同一形状・フットプリント） — 相違点: Package, Input Type, Power Dissipation, Architecture, Resolution.
クイック比較ツール — 並列比較する代替部品を選択:
ADS5220PFBR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS5220PFBTG4
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS6122IRGZR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS5220PFBRG4 最大定格＆電気的特性
| 分解能 | 12 bit |
| Sample Rate | 40 MSPS |
| Number of Input Channels | 1 |
| Input Type | Differential, Single-Ended |
| Data Interface | Parallel |
| Architecture | Pipelined |
| S/H:ADC Ratio | 1:1 |
| Number of A/D Converters | 1 |
| Reference Type | Internal or External |
| Signal-to-Noise Ratio (SNR) | 70 dB |
| Spurious-Free Dynamic Range (SFDR) | 88 dBFS |
| Differential Nonlinearity (DNL) | 0.3 LSB (typical) |
| Supply Voltage (Analog + Digital) | +3.3 V (single supply) |
| Power Dissipation | 195 mW (typical at 40 MSPS) |
| 動作温度範囲 | -40 °C to +85 °C |
| パッケージ | 48-pin TQFP (PFB) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| Lead-Free | Yes |
ADS5220PFBRG4 ピン構成
| ピン 1 | AVDD — Analog +3.3 V supply |
| ピン 2 | IN — Analog input (positive) |
| ピン 3 | INB — Complementary analog input |
| ピン 4 | AGND — Analog ground |
| ピン 5 | REF — Reference voltage input/output |
| ピン 6 | REFGND — Reference ground |
| ピン 7 | VREF — Internal reference bypass |
| ピン 8 | AGND — Analog ground |
| ピン 9 | AVDD — Analog +3.3 V supply |
| ピン 10 | CLK — Sample clock input |
| ピン 11 | CLKB — Complementary sample clock input |
| ピン 12 | AGND — Analog ground |
| ピン 13 | OE — Output enable (active-high logic input) |
| ピン 14 | DVDD — Digital +3.3 V supply |
| ピン 15 | DGND — Digital ground |
| ピン 16 | D0 — Parallel CMOS data output, bit 0 (LSB) |
| ピン 17 | D1 — Parallel CMOS data output, bit 1 |
| ピン 18 | D2 — Parallel CMOS data output, bit 2 |
| ピン 19 | D3 — Parallel CMOS data output, bit 3 |
| ピン 20 | D4 — Parallel CMOS data output, bit 4 |
| ピン 21 | D5 — Parallel CMOS data output, bit 5 |
| ピン 22 | D6 — Parallel CMOS data output, bit 6 |
| ピン 23 | D7 — Parallel CMOS data output, bit 7 |
| ピン 24 | D8 — Parallel CMOS data output, bit 8 |
| ピン 25 | D9 — Parallel CMOS data output, bit 9 |
| ピン 26 | D10 — Parallel CMOS data output, bit 10 |
| ピン 27 | D11 — Parallel CMOS data output, bit 11 (MSB) |
| ピン 28 | DGND — Digital ground |
| ピン 29 | DVDD — Digital +3.3 V supply |
| ピン 30 | NC — Not connected (per datasheet) |
| ピン 31 | NC — Not connected (per datasheet) |
| ピン 32 | NC — Not connected (per datasheet) |
| ピン 33 | NC — Not connected (per datasheet) |
| ピン 34 | NC — Not connected (per datasheet) |
| ピン 35 | NC — Not connected (per datasheet) |
| ピン 36 | NC — Not connected (per datasheet) |
| ピン 37 | NC — Not connected (per datasheet) |
| ピン 38 | NC — Not connected (per datasheet) |
| ピン 39 | NC — Not connected (per datasheet) |
| ピン 40 | NC — Not connected (per datasheet) |
| ピン 41 | NC — Not connected (per datasheet) |
| ピン 42 | NC — Not connected (per datasheet) |
| ピン 43 | NC — Not connected (per datasheet) |
| ピン 44 | NC — Not connected (per datasheet) |
| ピン 45 | NC — Not connected (per datasheet) |
| ピン 46 | NC — Not connected (per datasheet) |
| ピン 47 | NC — Not connected (per datasheet) |
| ピン 48 | NC — Not connected (per datasheet) |
主な用途
ADS5220PFBRG4 の用途: 6 件s: Ultrasound Imaging Front-End, Communications IF Sampling, Portable Instrumentation Digitizers, Digital Oscilloscope Input Stage, CCD/CIS Image Sensor Digitisation, Industrial Process Control & Data Acquisition.
Ultrasound Imaging Front-End
The ADS5220PFBRG4's 12-bit resolution at 40 MSPS and 70 dB SNR align well with mid-range ultrasound beam-forming front-ends that digitise summed transducer channels at rates up to ~20 MHz baseband plus headroom. The 88 dBc SFDR keeps harmonic content from leaking into adjacent image slices, while 195 mW dissipation per channel enables dense multi-channel receivers without forced-air cooling. Designers typically pair the ADC with a low-noise differential driver (THS4503-class) and route the parallel CMOS outputs directly to an FPGA beam-former; this minimises latency in receive-mode signal chains where the ADS5220PFBRG4 acts as the per-channel quantiser.
おすすめ
Communications IF Sampling
In communications receivers the ADS5220PFBRG4 supports intermediate-frequency (IF) sampling of signals up to ~10-15 MHz with 40 MSPS throughput, allowing digitisation of the second IF without a final downconversion stage. The 70 dB SNR preserves symbol-error performance while 88 dBc SFDR prevents co-channel spurs from degrading receiver selectivity. Its parallel CMOS outputs map directly to an FPGA digital-down-conversion block, and the 48-TQFP (PFB) package remains compatible with telecom-board layouts originally designed for the TI ADS5xxx/ADS6xxx families.
おすすめ
Portable Instrumentation Digitizers
Battery-powered oscilloscope, spectrum analyser, and data-acquisition front-ends benefit from the ADS5220PFBRG4's +3.3 V single-supply operation and 195 mW typical dissipation, which preserve battery runtime and simplify thermal design. The 12-bit/40 MSPS combination provides enough vertical and horizontal resolution for general-purpose waveform capture up to ~10 MHz useful bandwidth, while 70 dB SNR ensures trustworthy amplitude measurements on noisy bench signals. USB-isolated digitizer designs often place this ADC between the front-end attenuator/amplifier stage and a microcontroller/FPGA that streams the parallel samples through USB.
おすすめ
Digital Oscilloscope Input Stage
The ADS5220PFBRG4 is an effective quantiser for a 20-30 MHz bandwidth digital-storage oscilloscope, where its 12-bit resolution enables vertical scales well above the typical 8-bit scope and 70 dB SNR captures small detail on large signals. A front-end attenuator/amplifier scales the input to the ADC's full-scale range, and the parallel CMOS output port feeds an FPGA that implements trigger, decimation, and display refresh logic. Choosing 48-TQFP (PFB) footprint lets designers reuse the layout across the ADS5220 family and the TI-recommended ADS6122 active replacement.
おすすめ
CCD/CIS Image Sensor Digitisation
Scanners, copiers, and industrial line-scan cameras use the ADS5220PFBRG4 to digitise the analog output stream of CCD or CMOS image sensors at pixel-clock rates up to 40 MSPS. The programmable input range accommodates the varying signal amplitudes of colour channels, while 70 dB SNR preserves the 12-bit dynamic range needed for high-quality image reproduction. The internal reference option reduces external components on space-constrained line-scan camera PCBs.
おすすめ
Industrial Process Control & Data Acquisition
Programmable Logic Controllers (PLCs) and industrial data-acquisition subsystems digitise 0-10 V or 4-20 mA-derived signals at moderate rates using the ADS5220PFBRG4. The -40 °C to +85 °C operating range matches industrial enclosure thermal envelopes, and the 48-TQFP (PFB) package supports wave-solder and selective-solder assembly on multi-channel backplanes. The single +3.3 V supply draws from the same rail as the host microcontroller, simplifying power-tree design for cost-sensitive factory-automation boards.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS5220PFBRG4 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS5220PFBR | ADS5220PFBTG4 | ADS6122IRGZR |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-TQFP (PFB) | 48-TQFP (PFB) | 48-TQFP (PFB) | 48-TQFP (PFB) |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit |
| Sample Rate | 40 MSPS | 40 MSPS | 40 MSPS | 40 MSPS |
| Supply Voltage | +3.3 V | +3.3 V | +3.3 V | +3.3 V |
| Lifecycle | Obsolete | Obsolete | Obsolete | Active |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined |
| Input Type | Differential, Single-Ended | Differential, Single-Ended | Differential, Single-Ended | Differential |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
| Data Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS / LVDS selectable |
主な差別化要因
- TI-recommended active replacement preserves pin-out and core specs （vs ADS6122IRGZR)
- Same-die drop-in alternatives exist within the TI ADS5220 family （vs ADS5220PFBR)
- Mid-bandwidth throughput at low dissipation （vs ADS8482IBRGZR)
設計ノート
Provide separate analog (AVDD) and digital (DVDD) +3.3 V supplies routed through ferrite beads or LC pi-filters from a common +3.3 V rail. Place a 10 µF tantalum (or 22 µF ceramic) bulk capacitor and a 0.1 µF ceramic bypass capacitor as close as possible to each AVDD and DVDD pin. Estimated: with 195 mW total dissipation and theta_JA of ~50 °C/W (typical 48-TQFP), the junction temperature rise above ambient is roughly 10 °C at 25 °C ambient, so no heatsink is required.
Place the input RC anti-alias network within 5 mm of the IN pin, and route the differential pair (IN/INB) symmetrically with 50 Ω characteristic impedance and a solid analog ground beneath. Keep the CLK trace short and surrounded by digital ground to limit coupling into the analog domain. A continuous analog ground plane (no splits) under the ADC and its driver amplifier is essential for achieving the 70 dB SNR and 88 dBc SFDR.
Do not violate the maximum analog input range (approximately 1.5 Vpp differential with mid-scale common mode of 1.65 V) - a single-ended input above the rails causes code saturation and long-term drift. Always terminate the clock on the source side with a 50 Ω match to avoid double-edge triggering, and ensure the OE pin is tied low if unused to prevent bus contention. Driving the IN pin through DC coupling without biasing to mid-scale will shift the codes away from the centre of the range.
Route the parallel CMOS data bus D0-D11 with matched-length traces (within ±0.5 cm) to minimise output skew, and place 33 Ω series damping resistors near the ADC outputs to suppress reflections into the FPGA. Isolate the analog (AVDD/AGND) and digital (DVDD/DGND) return paths back to the regulator ground; do not cross them under the ADC. Use a guard trace on the unused NC pins tied to AGND to reduce edge coupling.
コンプライアンス情報
RoHS-compliant and lead-free per the TI ADS5220 datasheet and verified distributor listings. AEC-Q100 automotive qualification not published. Halogen-free status not explicitly published - leave as 'unknown'.