ADV7128KR50 - 10-Bit 80 MHz Video DAC | Analog Devices
部品番号: ADV7128KR50 ✓ 生産中ADV7128KR50 概要
A video DAC is a specialized digital-to-analog converter that translates digital pixel values into analog video signals. Within the broader hierarchy of data converters, it belongs to the ADC/DAC category and then to the video DAC subcategory, where conversion speed, pixel-clock handling, TTL interface compatibility, and standardized analog output characteristics matter more than general-purpose precision DAC flexibility.
The ADV7128 integrates a high-speed 10-bit D/A converter, a standard TTL input interface, and a high-impedance analog current-source output on one monolithic CMOS chip. According to the manufacturer product page, operation requires only a +5 V power supply, an external 1.23 V reference, and a pixel-clock input. This integration reduces the external component count in a video generation path while preserving compatibility with established analog video systems.
The converter uses pipelined operation to support an 80 MHz pixel rate. The supplied product information identifies 10-bit resolution, TTL-compatible digital inputs, and RS-343A and RS-170 compatible outputs. These characteristics make the device suitable for high-definition television, high-resolution color graphics, digital video recording, and other systems that require parallel digital pixels and conventional composite or component-style video outputs.
As an analog output device, the ADV7128 should be evaluated for reference accuracy, output compliance, monitor impedance, cable loading, and the required video standard rather than only for sample rate. The external 1.23 V reference is central to the conversion chain, so its accuracy and noise directly influence the resulting analog video quality. Layout should also preserve a low-impedance return path between the DAC, reference source, and analog output network.
A key design consideration is that the ADV7128 is a legacy video converter rather than a general-purpose current-output DAC. Existing boards should preserve the manufacturer reference and output network, while new designs should verify compatibility with the target monitor and video timing standard. The verified material does not provide a complete pin table, current-output range, settling time, or thermal resistance, so those values must be confirmed from the manufacturer datasheet before release to production.
This page consolidates the verified manufacturer and distributor information, distinguishes the 80 MHz family description from the 50 MSPS wording used by one reseller, and provides application guidance, comparisons, and practical design notes that are not consolidated in a single manufacturer product listing.
ドロップイン代替品: ADV7128KR50 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
ADV7128JR50
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADV7128KR50-REEL
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADV7128KR50Z
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADV7128JR50Z
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADV7128KR50-REEL
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADV7128KR50 最大定格＆電気的特性
| Product Type | Video digital-to-analog converter |
| 分解能 | 10 bit |
| Maximum Pixel Rate | 80 MHz |
| サンプリングレート | 50 MSPS according to reseller product data |
| Architecture | Pipelined CMOS video DAC |
| Number of Converters | 1 |
| Digital Input Interface | 10-bit parallel TTL-compatible pixel input |
| Analog Output | High-impedance current-source output |
| Video Output Compatibility | RS-343A and RS-170 compatible |
| 電源電圧 | +5 V |
| Operating Supply Range | 4.75 V to 5.25 V |
| External Reference | 1.23 V |
| Required Clock Input | Pixel clock input |
| パッケージ | 28-pin SOIC |
| 実装タイプ | Surface mount |
| Construction | Monolithic CMOS |
ADV7128KR50 28-pin soic ピン配置ガイド
ADV7128KR50 (28-pin soic パッケージ) のピン配置。 このアナログコンポーネントは、入力、出力、および電源ピンを備えています。オフセットナル、補償、イネーブルピンの設定については、メーカーのデータシートを参照してください。信号調整やアンプ回路に最適です。
詳細なピン配置データはありません: ADV7128KR50.
詳細は データシート をご参照ください。
主な用途
ADV7128KR50 の用途: 6 件s: High-Definition Television Video Generation, High-Resolution Color Graphics, Digital Video Recording Equipment, Video Test and Measurement Equipment, Professional Video Monitoring, Industrial Video Control Panels.
High-Definition Television Video Generation
The ADV7128KR50 fits parallel digital video generation in HDTV equipment because it combines a 10-bit TTL-compatible pixel input with an 80 MHz pipelined video-DAC description and RS-343A or RS-170 compatible outputs. The converter is placed at the boundary between a digital video controller and the analog video circuitry, using the external 1.23 V reference for accurate code-to-current conversion. A single 4.75 V to 5.25 V supply simplifies the analog rail budget, while the 28-pin SOIC supports board layouts derived from established ADV7128 designs. The primary validation points are pixel-clock jitter, reference accuracy, output compliance, and termination compatibility with the selected television interface.
おすすめ
High-Resolution Color Graphics
The ADV7128KR50 is appropriate for high-resolution color graphics when a design requires a dedicated 10-bit parallel pixel interface and conventional high-impedance analog video output. Its stated 80 MHz pipelined rate provides timing margin for demanding raster and frame-buffer interfaces, while the RS-343A and RS-170 compatibility supports established graphics equipment. The DAC is positioned after the pixel and timing logic, with the external 1.23 V reference providing the conversion reference and the output stage connected to the monitor through the appropriate resistive network. Engineers should verify the exact 28-pin net assignment, allowable pixel rate for the selected grade, and monitor impedance before releasing a revised board.
おすすめ
Digital Video Recording Equipment
The ADV7128KR50 can be used in legacy digital video recording systems that accept 10-bit parallel pixels and require a current-source analog output. The 80 MHz family description is suitable for high-rate video conversion, and the TTL-compatible input allows connection to digital timing and line-rate logic without a low-voltage differential interface. The circuit should use a low-noise +5 V supply, the specified external 1.23 V reference, and an output network matched to the recorder or monitor section. The design review must confirm whether the exact KR50 order code supports the intended pixel clock throughout the recording format, rather than assuming that the family-level 80 MHz rating applies without qualification.
おすすめ
Video Test and Measurement Equipment
The ADV7128KR50 can serve as the programmable analog video source in test equipment that must reproduce 10-bit raster patterns or conventional video waveforms. Its TTL-compatible digital input and pipelined operation make it suitable for connection to pattern-generation logic, while the external reference allows the test system to control amplitude and code accuracy. In this application, the DAC output is usually followed by calibrated attenuation or termination before being routed to the device under test. Calibration depends on the 1.23 V reference and output network, so a stable reference, low-noise supply, controlled ground return, and repeatable monitor impedance are more valuable than merely maximizing pixel throughput.
おすすめ
Professional Video Monitoring
The ADV7128KR50 is applicable to professional video monitoring and signal-conversion equipment that relies on standard high-impedance analog video connections. The device provides a 10-bit digital input and an RS-343A or RS-170 compatible current-source output, enabling legacy monitor electronics to remain compatible with newer digital sources. It is typically used with downstream resistive dividers, termination, and gain stages rather than driving a monitor load directly. The 28-pin SOIC footprint enables retrofit work on boards designed around ADV7128, but the converter grade, reference quality, and clock rate must be checked against the monitor's supported resolution and refresh rate. A common error is assuming that digital resolution alone guarantees acceptable analog bandwidth.
おすすめ
Industrial Video Control Panels
The ADV7128KR50 can support industrial video-control and operator-interface subsystems that generate legacy composite video from digital graphics or camera data. The single +5 V operating range and 10-bit parallel interface simplify integration with TTL-based control logic, while the high-impedance current output feeds a conventional analog video stage. The external 1.23 V reference should be placed close to the converter, and the digital input timing must be checked for setup and hold margin at the intended pixel rate. Because the verified material does not provide the complete pinout or temperature limits, any new industrial design should validate the exact order code, environmental requirements, output compliance, and isolation behavior before production use.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADV7128KR50 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADV7128JR50 | ADV7128KR50-REEL | ADV7128KR50Z | ADV7128JR50Z |
|---|---|---|---|---|---|
| Package | 28-pin SOIC | 28-pin SOIC - same | 28-pin SOIC - same | 28-pin SOIC - same | 28-pin SOIC - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Pixel Rate | 80 MHz | 80 MHz family description | 80 MHz family description | 80 MHz family description | 80 MHz family description |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| External Reference | 1.23 V | 1.23 V | 1.23 V | 1.23 V | 1.23 V |
| Digital Input | 10-bit TTL-compatible parallel input | 10-bit TTL-compatible parallel input | 10-bit TTL-compatible parallel input | 10-bit TTL-compatible parallel input | 10-bit TTL-compatible parallel input |
| Video Output Compatibility | RS-343A and RS-170 compatible | RS-343A and RS-170 compatible | RS-343A and RS-170 compatible | RS-343A and RS-170 compatible | RS-343A and RS-170 compatible |
| Analog Output | High-impedance current-source output | High-impedance current-source output | High-impedance current-source output | High-impedance current-source output | High-impedance current-source output |
主な差別化要因
- Direct 10-bit parallel video conversion （vs ADV7128JR50)
- Established K-grade order code （vs ADV7128JR50Z)
- RS-343A and RS-170 output compatibility （vs ADV7128KR50-REEL)
- Single +5 V architecture with external 1.23 V reference （vs ADV7128KR50Z)
設計ノート
The ADV7128KR50 operates from a single 4.75 V to 5.25 V supply. Place the local supply bypass capacitors directly at the device's power and ground pins and use a low-noise source so switching ripple does not modulate the video output. The external 1.23 V reference should have a short, quiet route to the converter, with its return current referenced carefully to the analog ground network. Verify the actual pin names and recommended capacitor values in the manufacturer datasheet before finalizing the layout.
Keep the 10-bit pixel bus short and route it away from the sensitive analog output and reference nodes. Maintain a continuous ground reference beneath the converter and preserve a low-impedance return for the external 1.23 V reference. Video DAC layouts should avoid long traces between the converter and output network, use matched grounding practices, and keep test-point stubs small. Because the complete verified pin table was unavailable, do not infer analog, sync, clock, or supply connections from neighboring pins.
Do not assume that the 80 MHz ADV7128 family description automatically applies to every ADV7128 ordering code, because the supplied reseller material describes ADV7128KR50 as a 50 MSPS device. Confirm the maximum pixel clock, setup and hold timing, output-current limits, and temperature grade in the exact manufacturer documentation. Also verify the RS-343A or RS-170 output network and monitor termination; a compatible package does not by itself guarantee equivalent system-level video performance.
Treat the pixel clock as a high-speed digital signal and control its edge rate and jitter. Provide a clean clock source with return-path continuity, and avoid routing the clock adjacent to the analog output and external reference. If the design includes long interconnects, use appropriately terminated point-to-point routing rather than relying on the DAC input to correct reflections. Confirm source, destination, and controller timing at the maximum intended pixel rate before approving the system.
コンプライアンス情報
The supplied verified web data does not state RoHS, REACH, AEC-Q100, lead-free, halogen-free, or conflict-minerals status. These fields remain unknown rather than being inferred from the manufacturer's product page or the component's age.